Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms

• US 20060041872A1
• Filed: 10/04/2005
• Published: 02/23/2006
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, LLC
• Inventors: Barker, David, Steidel, Jon, Poznanovic, Daniel, Brooks, Jeffrey Paul, Krause, Lisa, Hammes, Jeffrey
• Granted Patent: US 7,703,085 B2
• Time in Patent Office: Days
• US Class Current: 717/140
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

Claims

1. A method of forming a unified executable comprising:

partitioning a control-data flow graph into an instruction processor portion and a reconfigurable hardware portion;

converting the reconfigurable hardware portion of the control-data flow graph into a hardware definition language portion and the instruction processor portion into an instruction processor object file;

converting the hardware definition language portion into a reconfigurable hardware bitstream;

converting the reconfigurable hardware bitstream into a bitstream object file that is readable by an instruction processor; and

integrating the bitstream object file with the instruction processor object file to form the unified executable.

2. The method of claim 1 further comprising:

converting a control flow graph representation into the control-data flow graph representation.

3. The method of claim 2 further comprising:

converting a high level language source code into the control flow graph representation.

4. A system for forming a unified executable that is executable on a hybrid reconfigurable hardware-instruction processor computer, said system comprising:

a partitioner to partition control-dataflow graph representations into a reconfigurable hardware portion and an instruction processor portion;

a control-dataflow graph to hardware definition language converter to convert the reconfigurable hardware portion of the control-dataflow graph representations to a hardware definition language file;

a hardware definition language to bitstream converter to convert the hardware definition language file to a bitstream file;

a bitstream to object file converter to convert the bitstream file into a bitstream object file; and

a linker to integrate the bitstream object file into the unified executable.

5. The system of claim 4 further comprising:

a control flow graph to control-dataflow graph converter to convert control flow graph representations into the control-dataflow graph representations.

6. The system of claim 5 further comprising:

a high-level language converter to convert a high-level language into the control flow graph representations.

7. A computer program product comprising:

a computer usable medium having computer readable program code embodied therein for causing a formation of a unified executable, the computer readable program code comprising;

computer readable program code for causing the computer to partition a control-data flow graph into an instruction processor portion and a reconfigurable hardware portion;

computer readable program code for causing the computer to convert the reconfigurable hardware portion of the control-data flow graph into a hardware definition language portion and the instruction processor portion into an instruction processor object file;

computer readable program code for causing the computer to convert the hardware definition language portion into a reconfigurable hardware bitstream;

computer readable program code for causing the computer to convert the reconfigurable hardware bitstream into a bitstream object file that is readable by an instruction processor; and

computer readable program code for causing the computer to integrate the bitstream object file with the instruction processor object file to form the unified executable.

8. The computer program product of claim 7 further comprising:

computer readable program code for causing the computer to convert a control flow graph into the control-data flow graph.

9. The computer program product of claim 8 further comprising:

computer readable program code for causing a computer to convert a high level language source code into the control flow graph representation.