Semiconductor device

• US 20060043377A1
• Filed: 10/25/2005
• Published: 03/02/2006
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Hoffman, Randy L., Herman, Gregory S.
• Granted Patent: US 7,462,862 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device can include a channel including an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table.

Claims

1. A semiconductor device, comprising:

a drain electrode;

a source electrode;

a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel.

2. The semiconductor device of claim 1, wherein the combination comprises indium gallium oxide.

3. The semiconductor device of claim 2, wherein the channel has a peak incremental channel mobility of at least about 40 cm²/V s with a turn-on voltage greater than or equal to about −

15 volts.

4. The semiconductor device of claim 2, wherein the channel has a peak incremental channel mobility of at least about 2 cm²/V s and a turn-on voltage of between about −

5 volts and +5 volts.

5. The semiconductor device of claim 2, wherein the indium gallium oxide is sputter deposited.

6. The semiconductor device of claim 2, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) of greater than about 0.5.

7. The semiconductor device of claim 2, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.1 to about 0.5.

8. The semiconductor device of claim 2, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.75 to about 0.95.

9. The semiconductor device of claim 2, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.2 to about 0.4.

10. The semiconductor device of claim 2, wherein the indium gallium oxide has an atomic ratio of In/(In+Ga) in a range of about 0.05 to about 0.95.

11. The semiconductor device of claim 1, wherein the channel includes one of an amorphous form, a single-phase crystalline form, and a mixed-phase crystalline form.

12. The semiconductor device of claim 1, wherein at least one of the drain electrode, the source electrode, the channel, the gate electrode, and the gate dielectric are substantially transparent.

13. The semiconductor device of claim 1, wherein the channel is substantially transparent.

14. The semiconductor device of claim 1, wherein the combination comprises tin oxide and a second 4+ cation selected from within the D block and the P block of the Periodic Table.

15. The semiconductor device of claim 1, wherein the combination is selected from a group consisting of:

tin titanium oxide;

tin germanium oxide; and

tin titanium germanium oxide.

16. A semiconductor device, comprising:

a drain electrode;

a source electrode;

means for a channel to electrically couple the drain electrode and the source electrode, the means including indium gallium oxide;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel.

17. A method of forming a semiconductor device, comprising:

providing a drain electrode;

providing a source electrode;

depositing a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table;

providing a gate electrode; and

providing a gate dielectric positioned between the gate electrode and the channel.

18. The method of claim 17, wherein the channel includes indium gallium oxide.

19. The method of claim 18, wherein the channel has a composition with an atomic ratio of In/(In+Ga) of at least about 0.5.

20. The method of claim 19, wherein the channel is annealed at a temperature of at least about 200 degrees Celsius.

21. The method of claim 18, wherein the channel has a composition with an atomic ratio of In/(In+Ga) in a range of about 0.1 to about 0.5.

22. The method of claim 21 further comprising annealing the channel at a temperature of less than or equal to about 200 degrees Celsius.

23. The method of claim 17, wherein the channel includes tin oxide and an oxide from a group consisting of titanium oxide, germanium oxide, and titanium germanium oxide.

24. The method of claim 17 further comprising annealing the channel.

25. The method of claim 17, wherein the drain electrode, the source electrode, the gate dielectric and the gate electrode are substantially transparent.

26. The method of claim 18, wherein depositing the channel includes:

vaporizing a precursor composition including indium oxide and gallium oxide; and

depositing the vaporized precursor composition using a physical vapor deposition technique.

27. The method of claim 26, wherein the physical vapor deposition technique includes one or more of dc sputtering, rf sputtering, magnetron sputtering, and ion beam sputtering.

28. The method of claim 17, wherein depositing the channel includes depositing a precursor composition with an ink-jet deposition technique.

29. The method of claim 17, including providing a substrate or substrate assembly;

and

forming the semiconductor device on the substrate or substrate assembly.

30. A display device, comprising:

a plurality of display elements configured to operate collectively to display images, where each of the display elements includes a semiconductor device configured to control light emitted by the display element, the semiconductor device including;

a drain electrode;

a source electrode;

a channel contacting the drain electrode and the source electrode, wherein the channel includes an oxide comprising a combination of isovalent cations selected from within the D block and the P block of the Periodic Table;

a gate electrode; and

a gate dielectric positioned between the gate electrode and the channel and configured to permit application of an electric field to the channel.