Thin film transistor having an etching protection film and manufacturing method thereof

• US 20060043447A1
• Filed: 09/01/2005
• Published: 03/02/2006
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Yamaguchi, Ikuhiro, Ishii, Hiromitsu, Hokari, Hitoshi, Yoshida, Motohiko
• Granted Patent: US 7,385,224 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor of the present invention includes a semiconductor thin film (8); a gate insulating film (7) formed on one surface of the semiconductor thin film (8); a gate electrode (6) formed to be opposite to the semiconductor thin film (8) through the gate insulating film (7); a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor thin film (8); a source region; a drain region; and a channel region. The thin film transistor further includes an insulating film (9) formed on a peripheral portion corresponding to at least the source region and the drain region of the semiconductor thin film (8), and having a contact hole (10, 11) through which at least a part of each of the source region and the drain region is exposed wherein the source electrode (15) and the drain electrode (16) are connected to the semiconductor thin film (8) through the contact hole (10, 11).

Claims

1. A thin film transistor comprising:

a semiconductor thin film including a source region, a drain region, and a channel region;

a gate insulating film formed on one surface of the semiconductor thin film;

a gate electrode formed to be opposite to the semiconductor thin film through the gate insulating film;

a source electrode and a drain electrode electrically connected to the semiconductor thin film;

the thin film transistor further comprising;

an insulating film formed on a peripheral portion at least in the source region and the drain region of the semiconductor thin film, and having a contact hole through which at least a part of each of the source region and the drain region is exposed, and

wherein the source electrode and the drain electrode are connected to the semiconductor thin film through the contact hole.

2. The thin film transistor according to claim 1, wherein the insulating film has a central portion corresponding to the channel region of the semiconductor thin film.

3. The thin film transistor according to claim 2, further comprising:

an ohmic contact layer formed on the source region of the semiconductor thin film (8) exposed from the contact hole; and

an ohmic contact layer formed on the drain region.

4. The thin film transistor according to claim 3, further comprising:

a source electrode that completely covers the ohmic contact layer; and

a drain electrode that completely covers the ohmic contact layer.

5. The thin film transistor according to claim 1, wherein the source electrode and the drain electrode are directly connected to the resistance-reduced surface of the semiconductor thin film.

6. The thin film transistor according to claim 1, wherein the semiconductor thin film has an end surface in a channel direction, and the protection film has the same shaped end surface as that of the semiconductor thin film.

7. The thin film transistor according to claim 1, wherein an upper insulating film having a contact hole placed at a position corresponding to the contact hole is formed on the insulating film.

8. The thin film transistor according to claim 7, wherein the surface of the region exposed from at least the contact hole of the semiconductor thin film is subjected to resistance reduction.

9. The thin film transistor according to claim 8, wherein the source electrode and the drain electrode are directly connected to the surface of the region exposed from the contact hole of the semiconductor thin film.

10. The thin film transistor according to claim 7, further comprising:

an ohmic contact layer connected to the semiconductor thin film through the contract hole formed on each of the upper insulating film and the protection film.

11. The thin film transistor according to claim 10, wherein the source electrode and the drain electrode are formed on the respective ohmic contact layers to completely cover the respective ohmic contact layers.

12. A thin film transistor comprising:

a semiconductor thin film

a gate insulating film formed on one surface of the semiconductor thin film;

a gate electrode formed to be opposite to the semiconductor thin film through the gate insulating film; and

an ohmic contact layer formed on each of a source region and a drain region of the semiconductor thin film;

the thin film transistor further comprising;

an insulating film formed on a channel region of the semiconductor thin film corresponding to the gate electrode, and

wherein the ohmic contact layer is formed to cover to an upper surface end portion of the insulating film, an upper surface of the semiconductor thin film, and an end surface of the semiconductor thin film in a channel direction.

13. The thin film transistor according to claim 12, wherein the semiconductor thin film has a width in the channel region larger than a width in each of the source region and the drain region.

14. The thin film transistor according to claim 12, further comprising a source electrode and a drain electrode to completely cover the ohmic contact layer.

15. The thin film transistor according to claim 14, further comprising an overcoat film that covers the source electrode and the drain electrode and the insulating film placed between the source electrode and the drain electrode.

16. A thin film transistor comprising:

a semiconductor thin film;

a gate insulating film formed on one surface of the semiconductor thin film;

a gate electrode formed to be opposite to the semiconductor thin film through the gate insulating film; and

a source electrode and a drain electrode electrically connected to the semiconductor thin film;

the thin film transistor further comprising;

an insulating film formed on a channel region of the semiconductor thin film corresponding to the gate electrode, and

wherein a surface of the semiconductor thin film exposed without being covered with the insulating film is subjected to resistance reduction, and the source electrode and the drain electrode are respectively formed to cover to an upper surface end portion of the insulating film, an upper surface of the semiconductor thin film, and an end surface of the semiconductor thin film in a channel direction.

17. The thin film transistor according to claim 16, wherein the semiconductor thin film has a width in the channel region larger than a width in each of the source region and the drain region.

18. The thin film transistor according to claim 16, wherein the source electrode and the drain electrode are directly connected to the resistance-reduced surface of the semiconductor thin film.

19. The thin film transistor according to claim 16, further comprising an overcoat film that covers the source electrode and the drain electrode and the insulating film placed between the source electrode and the drain electrode.

20. A thin film transistor manufacturing method comprising:

forming a gate electrode, a gate insulating film and a semiconductor thin film;

forming an insulating film on the semiconductor thin film;

etching the semiconductor thin film and the insulating film to form the insulating film that exposes at least a part of each of a source region and a drain region of the semiconductor thin film on at least peripheral portions of the source region and the drain region; and

forming the source electrode and the drain electrode connected to the semiconductor thin film exposed from the insulating film.

21. The thin film transistor manufacturing method according to claim 20, wherein the insulating film and the semiconductor thin film are continuously etched.

22. The thin film transistor manufacturing method according to claim 20, wherein a zinc oxide is used as a main material of the semiconductor thin film, and an alkali solution is used to etch the semiconductor thin film.

23. The thin film transistor manufacturing method according to claim 20, wherein the alkali solution is sodium hydroxide solution of 2 to 10 wt %.

24. The thin film transistor manufacturing method according to claim 20, wherein the semiconductor thin film and the insulating film are etched to form an insulating film on the peripheral portions of the source region and the drain region of the semiconductor thin film and a region corresponding to a channel region of the semiconductor thin film.

25. The thin film transistor manufacturing method according to claim 20, wherein the semiconductor thin film and the insulating film are etched, thereafter forming an upper layer insulating film that exposes at least a part of each of the source region and the drain region on the insulating film.

26. The thin film transistor manufacturing method according to claim 20, wherein the semiconductor thin film and the insulating film are etched, thereafter forming an ohmic contact layer on the semiconductor thin film exposed from the semiconductor thin film.

27. The thin film transistor manufacturing method according to claim 26, wherein the source electrode and the drain electrode are formed to completely cover each ohmic contact layer.

28. The thin film transistor manufacturing method according to claim 20, wherein a region where the source electrode and the drain electrode of the semiconductor thin film are connected is subjected to resistance reduction.

29. A thin film transistor manufacturing method comprising:

forming a gate electrode, a gate insulating film and a semiconductor thin film;

forming an insulating film on the semiconductor thin film;

etching the semiconductor thin film to form a semiconductor thin film whose channel region width is larger than a source region width and a drain region width;

forming an ohmic contact layer on the source region of the semiconductor thin film and an ohmic contact layer on the drain region of the semiconductor thin film, wherein the ohmic contact layer covers an end surface of the semiconductor thin film in a channel direction and two end surfaces parallel to the channel direction, respectively; and

forming a source electrode and a drain electrode on the ohmic contact layers respectively.

30. The thin film transistor manufacturing method according to claim 29, wherein a mask having a width smaller than a width of the insulting film is formed on the insulating film and the semiconductor thin film in etching the semiconductor thin film and the semiconductor thin film is etched using the insulating film and the mask as a mask.

31. A thin film transistor manufacturing method comprising:

forming a gate electrode, a gate insulating film and a semiconductor thin film;

forming an insulating film on the semiconductor thin film;

etching the semiconductor thin film to form a semiconductor thin film whose channel region width is larger than a source region width and a drain region width;

performing resistance reduction to surfaces of the source region and the drain region of the semiconductor thin film; and

forming a source electrode on the source region of the semiconductor thin film and a drain electrode on the drain region, wherein the source electrode and the drain electrode cover an end surface of the semiconductor thin film in a channel direction and two end surfaces parallel to the channel direction, respectively.

32. The thin film transistor manufacturing method according to claim 31, wherein a mask having a width smaller than a width of the insulating film is formed on the insulating film and the semiconductor thin film and the semiconductor thin film is etched using the insulating film and the mask as a mask.

33. A thin film transistor manufacturing method comprising:

forming a gate electrode, a gate insulating film and a semiconductor thin film;

forming an insulating film on the semiconductor thin film;

etching the semiconductor thin film using the insulating film as a mask to form a semiconductor thin film;

forming a contact hole that exposes each of a source region and a drain region of the semiconductor thin film on the insulating film; and

forming a source electrode connected to the source region of the semiconductor thin film and a drain electrode connected to the drain region of the semiconductor thin film.

34. The thin film transistor manufacturing method according to claim 33,

wherein an upper insulating film is formed on the insulating film and the semiconductor thin film before the source electrode and the drain electrode are formed, and

wherein a contact hole is formed in a region corresponding to each contact hole of the upper insulating film.

35. The thin film transistor manufacturing method according to claim 33, wherein an ohmic contact layer is formed on each of the source region and the drain region of the semiconductor thin film before the source electrode and the drain electrode are formed.