Gate coupling in floating-gate memory cells

• US 20060043458A1
• Filed: 09/02/2004
• Published: 03/02/2006
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rudeck, Paul J.
• Granted Patent: US 7,115,458 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

Claims

1. A method of fabricating floating-gate memory cells, comprising:

forming an isolation region in a semiconductor substrate;

forming a tunnel dielectric layer overlying the substrate on opposing sides of the isolation region;

forming a floating-gate layer overlying the tunnel dielectric layer and overlying the isolation region;

forming a trench in the floating-gate layer overlying the isolation region, wherein the isolation region remains covered by the floating-gate layer after forming the trench;

forming spacers on sidewalls of the trench, leaving a portion of the floating-gate layer exposed between the spacers;

removing the exposed portion of the floating-gate layer;

forming an intergate dielectric layer overlying the floating-gate layer; and

forming a control-gate layer overlying the intergate dielectric layer.

2. The method of claim 1, wherein forming an isolation region further comprises forming a shallow trench isolation region.

3. The method of claim 1, wherein forming a tunnel dielectric layer overlying the substrate further comprises growing the tunnel dielectric layer on the substrate.

4. The method of claim 1, wherein forming a floating-gate layer overlying the tunnel dielectric layer and overlying the isolation region further comprises forming a first layer overlying and adjoining the tunnel dielectric layer and forming a second layer overlying and adjoining the first layer and the isolation region.

5. The method of claim 4, further comprising forming the second layer overlying and adjoining a second isolation region, wherein the isolation region and the second isolation region are formed on opposing sides of the tunnel dielectric layer.

6. The method of claim 1, wherein forming a trench in the floating-gate layer overlying the isolation region further comprises:

forming a hard mask layer overlying the floating-gate layer;

forming and patterning a second mask layer overlying the hard mask layer, thereby exposing a first area of the hard mask layer overlying the isolation region;

removing the exposed first area of the hard mask layer, thereby exposing a first area of the floating-gate layer overlying the isolation region; and

removing less than an entire thickness of the floating-gate layer in the exposed first area of the floating-gate layer.

7. The method of claim 6, wherein removing less than an entire thickness of the floating-gate layer in the exposed first area of the floating-gate layer further comprises etching the exposed first area of the floating-gate layer for a predetermined period of time.

8. The method of claim 6, wherein removing less than an entire thickness of the floating-gate layer in the exposed first area of the floating-gate layer further comprises removing ½

or more of the thickness.

9. The method of claim 8, wherein removing less than an entire thickness of the floating-gate layer in the exposed first area of the floating-gate layer further comprises removing approximately ¾

of the thickness.

10. The method of claim 1, wherein forming spacers on sidewalls of the trench further comprises forming a layer of material overlying the floating-gate layer and anisotropically removing horizontal portions of the layer of material.

11. The method of claim 10, wherein a patterned hard mask layer is overlying the floating-gate layer and the layer of material is formed overlying the hard mask layer and the floating-gate layer.

12. The method of claim 1, wherein removing the exposed portion of the floating-gate layer further comprises removing the exposed portion of the floating-gate layer using the isolation region as a stopping layer.

13. A method of forming a floating-gate memory cell, comprising:

forming a tunnel dielectric layer overlying an active region of a semiconductor substrate interposed between two isolation regions;

forming a floating-gate layer overlying the isolation regions and the tunnel dielectric layer;

removing a first portion of the floating-gate layer overlying a first of the isolation regions, wherein the first isolation region remains covered by the floating-gate layer after removing the first portion;

removing a second portion of the floating-gate layer overlying a second of the isolation regions, wherein the second isolation region remains covered by the floating-gate layer after removing the second portion;

removing a third portion of the floating-gate layer overlying the first isolation region to expose a portion of the first isolation region;

removing a fourth portion of the floating-gate layer overlying the second isolation region to expose a portion of the second isolation region;

forming an intergate dielectric layer overlying the floating-gate layer and the isolation regions; and

forming a control-gate layer overlying the intergate dielectric layer.

14. The method of claim 13, further comprising:

forming the two isolation regions on opposing sides of the active region of the substrate by forming two trenches in the substrate and filling the trenches with dielectric material.

15. The method of claim 13, wherein forming a floating-gate layer overlying the isolation regions and the tunnel dielectric layer further comprises forming a first polysilicon layer overlying the tunnel dielectric layer and forming a second polysilicon layer overlying the first polysilicon layer and the isolation regions.

16. The method of claim 13, wherein removing a first portion of the floating-gate layer overlying a first of the isolation regions further comprises forming a trench in the floating-gate layer.

17. The method of claim 16, wherein the trench has a width substantially equal to a width of the first isolation region.

18. The method of claim 17, wherein the trench has a depth equal to approximately ½

or more of a thickness of the floating-gate layer overlying the first isolation region prior to removing the first portion.

19. The method of claim 13, wherein removing a second portion of the floating-gate layer overlying a second of the isolation regions further comprises forming a trench in the floating-gate layer.

20. The method of claim 19, wherein the trench has a width substantially equal to a width of the second isolation region.

21. The method of claim 20, wherein the trench has a depth equal to approximately ½

or more of a thickness of the floating-gate layer overlying the second isolation region prior to removing the second portion.

22. The method of claim 13, wherein removing a third portion of the floating-gate layer overlying the first isolation region to expose a portion of the first isolation region further comprises etching the third portion of the floating-gate layer using the first isolation region as a stopping layer and wherein removing a fourth portion of the floating-gate layer overlying the second isolation region to expose a portion of the second isolation region further comprises etching the fourth portion of the floating-gate layer using the second isolation region as a stopping layer.

23. The method of claim 13, wherein the third portion of the floating-gate layer has a width less than a width of the first portion of the floating-gate layer and wherein the fourth portion of the floating-gate layer has a width less than a width of the second portion of the floating-gate layer.

24. The method of claim 13, wherein the width of the third portion is approximately ½

or less the width of the first portion and the width of the fourth portion is approximately ½

or less the width of the second portion.

25. The method of claim 13, wherein the width of the third portion is approximately ⅓

or less the width of the first portion and the width of the fourth portion is approximately ⅓

or less the width of the second portion.

26. A floating-gate memory cell, comprising:

a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;

a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer.

27. The floating-gate memory cell of claim 26, wherein the first and second upper sidewalls are substantially aligned with edges of the first and second isolation regions, respectively.

28. The floating-gate memory cell of claim 26, wherein the lower sidewalls have a height that is less than or equal to a height of the upper sidewalls.

29. The floating-gate memory cell of claim 28, wherein the height of the upper sidewalls is approximately 1 to 3 times the height of the lower sidewalls.

30. The floating-gate memory cell of claim 26, wherein the floating-gate layer comprises one or more layers of material capable of storing a charge.

31. The floating-gate memory cell of claim 30, wherein the floating-gate layer comprises first and second polysilicon layers.

32. The floating-gate memory cell of claim 26, wherein the floating-gate memory cell is arranged and configured as part of a NAND array of memory cells.

33. A floating-gate memory cell, comprising:

a tunnel dielectric layer overlying a semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer.

34. The floating-gate memory cell of claim 33, wherein the lower portion of the floating-gate layer is in closer proximity to a lower portion of a floating-gate layer of an adjacent floating-gate memory cell than the upper portion of the floating-gate layer is in relation to an upper portion of the floating-gate layer of the adjacent floating-gate memory cell.

35. The floating-gate memory cell of claim 33, wherein the tunnel dielectric layer is a silicon oxide layer.

36. The floating-gate memory cell of claim 35, wherein the silicon oxide layer is thermally grown on a monocrystalline silicon substrate.

37. The floating-gate memory cell of claim 33, wherein the floating-gate layer is overlying and adjoining the tunnel dielectric layer.

38. The floating-gate memory cell of claim 33, wherein the floating-gate layer comprises more than one layer of material.

39. The floating-gate memory cell of claim 38, wherein the floating-gate layer comprises a first polysilicon layer adjoining the tunnel dielectric layer and interposed between two isolation regions, and a second polysilicon layer adjoining the first polysilicon layer and overlying at least a portion of each of the two isolation regions.

40. The floating-gate memory cell of claim 39, wherein the first and second polysilicon layers are each conductively doped at a time selected from the group consisting of during formation and after formation.

41. The floating-gate memory cell of claim 33, wherein the intergate dielectric layer is overlying and adjoining the floating-gate layer.

42. The floating-gate memory cell of claim 33, wherein the intergate dielectric layer comprises more than one layer of dielectric material.

43. The floating-gate memory cell of claim 33, wherein the control-gate layer is overlying and adjoining the intergate dielectric layer.

44. The floating-gate memory cell of claim 33, wherein the control-gate layer comprises more than one layer of conductive material.

45. The floating-gate memory cell of claim 33, wherein the floating-gate memory cell is arranged and configured as part of a NAND array of memory cells.

46. A memory device, comprising:

an array of floating-gate memory cells; and

circuitry for control and/or access of the array of floating-gate memory cells;

wherein the at least one memory cell of the array of floating-gate memory cells comprises;

a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;

a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer.

47. The memory device of claim 46, wherein the array of floating-gate memory cells are arranged and configured as a NAND array of floating-gate memory cells.

48. A memory device, comprising:

an array of floating-gate memory cells; and

circuitry for control and/or access of the array of floating-gate memory cells;

wherein the at least one memory cell of the array of floating-gate memory cells comprises;

a tunnel dielectric layer overlying a semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer.

49. The memory device of claim 48, wherein the array of floating-gate memory cells are arranged and configured as a NAND array of floating-gate memory cells.

50. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

an array of floating-gate memory cells, at least one memory cell comprising;

a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;

a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer; and

circuitry for control and/or access of the array of floating-gate memory cells.

51. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

an array of floating-gate memory cells, at least one memory cell comprising;

a tunnel dielectric layer overlying a semiconductor substrate;

a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;

an intergate dielectric layer overlying the floating-gate layer; and

a control-gate layer overlying the intergate dielectric layer; and

circuitry for control and/or access of the array of floating-gate memory cells.