Interposers for chip-scale packages and intermediates thereof

• US 20060043477A1
• Filed: 10/13/2005
• Published: 03/02/2006
• Est. Priority Date: 11/11/2002
• Status: Active Grant

• Current Assignee: Salman Akram
• Original Assignee: Salman Akram
• Inventors: Akram, Salman
• Granted Patent: US 7,368,812 B2
• Time in Patent Office: Days
• US Class Current: 257/337
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/90 Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor

Abstract

A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. The interposer may also include a rerouting element laminated over the remainder of the interposer and including one or more dielectric layers, as well as a conductive layer for rerouting the bond pad locations of a semiconductor device with which the interposer is to be assembled. The interposers may be fabricated on a “wafer scale.” Accordingly, a semiconductor device assembly may include a first, semiconductor device-carrying substrate and a second, interposer-comprising substrate. Regions of the second substrate that comprise the boundaries between adjacent interposers may be thinner than other regions of the second substrate, including the regions from which the interposers are formed.

Claims

1. An interposer for use in a chip-scale package having at least one semiconductor device, the interposer comprising:

a substrate having a coefficient of thermal expansion substantially the same as a coefficient of thermal expansion of a semiconductor device of the chip-scale package, the substrate including a plurality of apertures formed therethrough at locations corresponding to locations of bond pads of the semiconductor device, each aperture having a length;

an electrically insulative lining covering at least one surface of each aperture of the plurality of apertures;

conductive material at least partially filling each aperture and extending substantially along the length of each aperture;

a dielectric film positioned over the substrate and including a plurality of apertures aligned with corresponding apertures of the substrate;

a layer comprising conductive material over the dielectric film and including a plurality of laterally extending conductive traces in communication with corresponding apertures of the dielectric film for laterally rerouting the locations of bond pads of the semiconductor device;

another dielectric film over the layer comprising conductive material and including a plurality of apertures positioned over rerouted bond pad locations of the plurality of laterally extending conductive traces of the layer comprising conductive material.

2. The interposer of claim 1, wherein the substrate comprises silicon.

3. The interposer of claim 1, further comprising:

an underfill material between the substrate and the dielectric film.

4. The interposer of claim 1, wherein the plurality of apertures of the substrate are located for alignment over bond pads arranged linearly over a center of the semiconductor device.

5. The interposer of claim 4, wherein the rerouted bond pads are arranged in an array.

6. The interposer of claim 1, wherein the dielectric layer and the another dielectric layer comprise polymer.

7. The interposer of claim 1, including a hollow region within the conductive material at least partially filling each aperture formed through the substrate.

8. The interposer of claim 1, further comprising a plurality of contacts, each contact of the plurality of contacts aligned with an aperture of the plurality of apertures of the substrate and communicating with the conductive material in the aperture.

9. The interposer of claim 8, wherein each contact of the plurality of contacts is also aligned with an aperture of the plurality of apertures of the dielectric layer.

10. The interposer of claim 9, wherein each contact of the plurality of contacts is secured to a corresponding conductive trace of the plurality of laterally extending conductive traces.

11. The interposer of claim 1, wherein the substrate comprises a portion of a large-scale substrate for forming a plurality of interposers.

12. The interposer of claim 11, wherein the large-scale substrate comprises a wafer of semiconductor material.

13. A semiconductor device assembly, comprising:

a first large-scale substrate comprising a plurality of semiconductor devices formed thereon, each semiconductor device of the plurality of semiconductor devices including at least one bond pad on an active surface thereof;

a second large-scale substrate positioned adjacent the first large-scale substrate and including a plurality of interposers, boundaries between interposers of the plurality of interposers having a reduced thickness relative to the interposers, each interposer of the plurality of interposers corresponding to a semiconductor device of the plurality of semiconductor devices and including at least one aperture formed therethrough, the at least one aperture aligned over the at least one bond pad of the corresponding semiconductor device; and

conductive material located within at least a portion of the at least one aperture, the conductive material extending substantially along a length of the at least one aperture and being bonded to the at least one bond pad.

14. The semiconductor device assembly of claim 13, wherein the first large-scale substrate comprises a wafer of semiconductor material.

15. The semiconductor device assembly of claim 13, wherein the second large-scale substrate comprises a wafer of semiconductor material.

16. The semiconductor device assembly of claim 13, wherein the second large-scale substrate includes thin regions between adjacent interposers of the plurality of interposers.

17. The semiconductor device assembly of claim 16, wherein the thin regions extend substantially through the second large-scale substrate.

18. The semiconductor device assembly of claim 13, wherein each interposer includes at least one contact pad positioned over the at least one aperture in communication with the conductive material within at least the portion of the at least one aperture.

19. The semiconductor device assembly of claim 13, further comprising an electrically insulative material disposed between the first large-scale substrate and the second large-scale substrate.

20. The semiconductor device assembly of claim 13, including a hollow area within the conductive material within the at least one aperture of each interposer.

21. The semiconductor device assembly of claim 13, further comprising at least one conductive structure protruding from each interposer on an opposite side thereof from the corresponding semiconductor device and communicating with the at least one bond pad of the corresponding semiconductor device.

22. The semiconductor device assembly of claim 13, wherein at least some interposers of the plurality of interposers include laterally extending conductive traces communicating with the conductive material in at least the portion of the at least one aperture thereof.

23. The semiconductor device assembly of claim 13, further comprising an additional interposer layer positioned adjacent each interposer of the plurality of interposers, opposite each interposer from the corresponding semiconductor device, the additional interposer layer including a laterally extending conductive trace and at least one contact pad, the at least one contact pad having a different lateral position relative to a plane of the corresponding semiconductor device than the at least one bond pad of the corresponding semiconductor device.

24. The semiconductor device assembly of claim 23, wherein the additional interposer layer comprises a material having substantially the same coefficient of thermal expansion as a material of the first and second large-scale substrates.

25. The semiconductor device assembly of claim 24, wherein the additional interposer layer comprises a semiconductor material.

26. The semiconductor device assembly of claim 23, wherein the additional interposer layer comprises polyimide.