Semiconductor device and fabrication method of the same

• US 20060043480A1
• Filed: 11/19/2004
• Published: 03/02/2006
• Est. Priority Date: 09/01/2004
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamashita, Atsuko, Tsuchitani, Masanobu, Matsuda, Tetsuo, Okumura, Hideki
• Application Number:
  US10/991,433
• Publication Number:
  US 20060043480A1
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device comprises a semiconductor layer which includes a terminate end part and a cell formation part that is surrounded by this end part, and a plurality of guard rings each of which is formed at the end part to surround the cell formation part. These guard rings are made shallower and smaller in width as they get near to the guard ring that resides at the outside position.

Claims

1. A semiconductor device comprising:

a semiconductor layer including a terminate end part and a cell formation part as surrounded by this end part; and

a plurality of guard rings each being formed at the end part to surround said cell formation part and being arranged to become shallower and smaller in width as getting near to a guard ring placed outside.

2. The device according to claim 1, wherein the guard rings are made larger in interval between neighboring ones thereof as getting near to the guard ring placed outside.

3. The device according to claim 1, wherein said plurality of guard rings have a structure with an epitaxial growth layer being buried in a plurality of trenches as provided at said end part.

4. The device according to claim 1, wherein

said semiconductor layer is disposed above a surface of a semiconductor substrate of a first conductivity type,

said cell formation part includes a plurality of first semiconductor regions of the first conductivity type and a plurality of second semiconductor regions of a second conductivity type as disposed above the surface of said semiconductor substrate, and

in said cell formation part, said plurality of first semiconductor regions and said second semiconductor regions are alternately repeatedly laid out in a direction parallel to the surface of said semiconductor substrate.

5. The device according to claim 4, wherein said plurality of first semiconductor regions have a structure formed by providing a plurality of first trenches in a single-crystalline semiconductor layer of the first conductivity type as disposed above the surface of said semiconductor substrate,

said plurality of second semiconductor regions have a structure with an epitaxial growth layer of the second conductivity type being buried in said plurality of first trenches, and

said plurality of guard rings have a structure with an epitaxial growth layer of the second conductivity type being buried in a plurality of second trenches as provided at said end part.

6. The device according to claim 1, wherein said end part includes a channel stopper region at a further outside position of said plurality of guard rings.

7. The device according to claim 1, wherein said cell formation part includes one or more power semiconductor elements.

8. The device according to claim 4, wherein said cell formation part includes one or more power semiconductor elements having a super junction structure, said plurality of first semiconductor regions and said second semiconductor regions constituting said super junction structure.

9. A semiconductor device comprising:

a semiconductor layer including a terminate end part and a cell formation part as surrounded by this end part; and

a plurality of guard rings each being formed at the end part to surround said cell formation part and being arranged to become shallower and larger in interval between neighboring ones thereof as getting near to a guard ring placed outside.

10. The device according to claim 9, wherein said plurality of guard rings have a structure with an epitaxial growth layer being buried in a plurality of trenches as provided at said end part.

11. The device according to claim 9, wherein

said semiconductor layer is disposed above a surface of a semiconductor substrate of a first conductivity type,

said cell formation part includes a plurality of first semiconductor regions of the first conductivity type and a plurality of second semiconductor regions of a second conductivity type as disposed above the surface of said semiconductor substrate, and

in said cell formation part, said plurality of first semiconductor regions and said second semiconductor regions are alternately repeatedly laid out in a direction parallel to the surface of said semiconductor substrate.

12. The device according to claim 11, wherein said plurality of first semiconductor regions have a structure formed by providing a plurality of first trenches in a single-crystalline semiconductor layer of the first conductivity type as disposed above the surface of said semiconductor substrate,

said plurality of second semiconductor regions have a structure with an epitaxial growth layer of the second conductivity type being buried in said plurality of first trenches, and

said plurality of guard rings have a structure with an epitaxial growth layer of the second conductivity type being buried in a plurality of second trenches as provided at said end part.

13. The device according to claim 9, wherein said end part includes a channel stopper region at a further outside position of said plurality of guard rings.

14. The device according to claim 9, wherein said cell formation part includes one or more power semiconductor elements.

15. The device according to claim 11, wherein said cell formation part includes one or more power semiconductor elements having a super junction structure, said plurality of first semiconductor regions and said second semiconductor regions constituting said super junction structure.

16. A method for fabricating a semiconductor device comprising:

forming a to-be-processed film to be processed into a mask on a surface of a semiconductor layer including a terminate end part and a cell formation part as surrounded by this end part;

forming at a portion of said to-be-processed film corresponding to said end part a plurality of openings surrounding a portion of said to-be-processed film corresponding to said cell formation part and being made smaller in width as getting near to an opening placed outside;

selectively etching said semiconductor layer while letting said to-be-processed film with said plurality of openings formed therein be as a mask to thereby form in said end part a plurality of trenches being made shallower and smaller in width as getting near to a trench placed outside; and

burying an epitaxial growth layer in said plurality of trenches to thereby form in said end part a plurality of guard rings.

17. The method according to claim 16, wherein said plurality of openings are made larger in interval of neighboring ones thereof as getting near to an opening placed outside.

18. The method according to claim 16, wherein said semiconductor layer is a single-crystalline semiconductor layer of a first conductivity type as disposed above a surface of a semiconductor substrate,

in said forming a plurality of openings, a plurality of other openings are formed at the portion of said to-be-processed film corresponding to said cell formation part,

in said selectively etching said semiconductor layer to form a plurality of trenches, a plurality of other trenches causing a portion between neighboring trenches to become a first semiconductor region are formed in said cell formation part, and

in said burying an epitaxial growth layer to form a plurality of guard rings, said epitaxial growth layer of a second conductivity type is buried in said plurality of other trenches to thereby form in said cell formation part a plurality of second semiconductor regions as alternately repeatedly laid out with said first semiconductor regions in a direction parallel to the surface of said semiconductor substrate.

19. The method according to claim 16, wherein

said semiconductor layer is a single-crystalline semiconductor layer of a first conductivity type as disposed above a surface of a semiconductor substrate, and

said method further comprises, before or after said forming a plurality of openings and said selectively etching said semiconductor layer to form a plurality of trenches and said burying an epitaxial growth layer to form a plurality of guard rings:

forming a plurality of other openings at the portion of said to-be-processed film corresponding to said cell formation part;

selectively etching said semiconductor layer while letting said to-be-processed film with said plurality of other openings formed therein be as a mask to thereby form in said cell formation part a plurality of other trenches causing a portion between neighboring trenches to become a first semiconductor region; and

burying in said plurality of other trenches an epitaxial growth layer of a second conductivity type to thereby form in said cell formation part a plurality of second semiconductor regions as alternately repeatedly laid out with said first semiconductor regions in a direction parallel to the surface of said semiconductor substrate.

20. The method according to claim 16, further comprising:

forming one or more power semiconductor elements in said cell formation part.