Variable threshold transistor for the Schottky FPGA and multilevel storage cell flash arrays

• US 20060044018A1
• Filed: 04/02/2004
• Published: 03/02/2006
• Est. Priority Date: 04/02/2004
• Status: Abandoned Application

• Current Assignee: Super Talent Electronics, Inc.
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Chang, Augustine W.
• Application Number:
  US10/817,201
• Publication Number:
  US 20060044018A1
• Time in Patent Office: Days
• US Class Current: 326/101
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/0956 Schottky diode FET logic H03K19/096 takes precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions. It acts as an analog device to store directly nonvolatile information in SCL gates. It couples the diode tree logic functions. Finally, it stores and operates large amount of information efficiently. The mixed SCL type FPGA and MLC storages shall emerge as the most compact logic and memory arrays in Si technology. Low power, high performance, and high capacity ICs are designed to mix and replace conventional CMOS-TTL circuits. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced.

Claims

1. A mixed signal circuit comprising:

a plurality of fixed threshold and variable threshold transistors;

a plurality of Schottky barrier diodes;

a plurality of poly silicon film resistors;

a plurality of capacitors; and

a plurality of wiring tracks, wherein all of the elements are on a single substrate to form integrated circuits with implementing macro functions.

2. The mixed signal circuit of claim 1 wherein the circuit is software driven.

3. The mixed signal circuit of claim 2 wherein software is provided to adjust the threshold of the variable threshold transistors.

4. The mixed signal circuit of claim 2 wherein software is provided to form reconfigurable logic gate array circuit units.

5. The mixed signal circuit of claim 2 wherein software is provided to complete certain network connections among various units in the single diagram.

6. The mixed signal circuit of claim 2 wherein the software includes state tables, virtual machines, setup or initialization and test procedures, data access, transport, and storage algorithms.

7. The mixed signal circuit of claim 1 wherein the circuit is hardware driven, wherein the hardware comprises hardwired Schottky CMOS Logic (SCL) gate array and memory units, IO transceivers, and terminators.

8. The mixed signal circuit of claim 7 wherein the hardware comprises software driven SCL gate arrays, IO transceivers, terminators, capacitors and wherein a switch transistor is of VT type.

9. The mixed signal circuit of claim 7 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit act as analog signal comparator.

10. The mixed signal circuit of claim 7 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL gate may perform a nonvolatile latch function.

11. The mixed signal circuit of claim 7 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit may process multi-value logic operation with binary, ternary and quaternary operators.

12. The mixed signal circuit of claim 7 which includes software driven CMOS-TTL gate arrays, IO transceivers, terminators and capacitors.

13. The mixed signal circuit of claim 7 which includes hardwired conventional logic and memory units including but not limited to CMOS-TTL gate arrays, Register files, embedded RAM, ROM and Flash cores.

14. The mixed signal circuit of claim 7 which includes dedicated programming facilities of voltage and current sources, clock and oscillators, state machines and counters, to implement and control both cell wise and block wise cell operations and which is shared to alter the charge storage or VT threshold of the selected device(s) in the logic and (Flash) memory circuitry.

15. The mixed signal circuit of claim 1 wherein the SBDs comprise a PN junction diode if SOI GaAs technologies are used.

16. The mixed signal circuit of claim 1 wherein the SBD can be coupled to input pads for Electrical Static Discharge protection.

17. The mixed signal circuit of claim 1 wherein the SBD can be coupled to the well for Latch-up suppression.

18. The mixed signal circuit of claim 1 wherein the SBD can be coupled to control the well biasing potential, therefore change I-V characteristics of CFETs within the well region with circuit operating conditions.

19. The mixed signal circuit of claim 3 wherein the SBDs are adaptable to other product applications including but not limited to DRAM, Flash, CAM, PLD, ROM, and embedded ASICs.

20. A mixed signal circuit comprising:

a plurality of fixed threshold and variable threshold transistors;

a plurality of Schottky barrier diodes;

a plurality of poly silicon film resistors;

a plurality of capacitors; and

a plurality of wiring tracks, wherein all of the elements are on a single substrate to form integrated circuits with implementing macro functions, wherein the circuit is software driven and wherein the at least a portion of the macro functions can be hardwired macroassets.

21. The mixed signal circuit of claim 20 wherein software is provided to adjust the threshold of the variable threshold transistors.

22. The mixed signal circuit of claim 20 wherein software is provided to form reconfigurable logic gate array circuit units.

23. The mixed signal circuit of claim 20 wherein software is provided to complete certain network connections among various units in the single diagram.

24. The mixed signal circuit of claim 20 wherein the software includes state tables, virtual machines, setup or initialization and test procedures, data access, transport and storage algorithms.

25. The mixed signal circuit of claim 20 wherein the circuit is hardware driven, wherein the hardware comprises hardwired Schottky CMOS Logic (SCL) gate array and memory units, IO transceivers, and terminators.

26. The mixed signal circuit of claim 25 wherein the hardware comprises software driven SCL gate arrays, IO transceivers, terminators, capacitors and wherein a switch transistor is of VT type.

27. The mixed signal circuit of claim 25 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit act as analog signal comparator.

28. The mixed signal circuit of claim 25, which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL gate may perform a nonvolatile latch function.

29. The mixed signal circuit of claim 25 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit may process multi-value logic operation with binary, ternary and quaternary operators.

30. The mixed signal circuit of claim 25 which includes software driven CMOS-TTL gate arrays, IO transceivers, terminators and capacitors.

31. The mixed signal circuit of claim 25 which includes hardwired conventional logic and memory units including but not limited to CMOS-TTL gate arrays, Register files, embedded RAM, ROM and Flash cores.

32. The mixed signal circuit of claim 25 which includes dedicated programming facilities of voltage and current sources, clock and oscillators, state machines and counters, to implement and control both cell wise and block wise cell operations and which is shared to alter the charge storage or VT threshold of the selected device(s) in the logic and (Flash) memory circuitry.

33. A mixed signal circuit comprising:

a plurality of fixed threshold and variable threshold transistors;

a plurality of Schottky barrier diodes;

a plurality of poly silicon film resistors;

a plurality of capacitors; and

a plurality of wiring tracks, wherein all the elements are on a single substrate to form integrated circuits with implementing macro functions, wherein a part of the elements are user programmed and part of the elements are factory programmable, wherein the circuit is software driven.

34. The mixed signal circuit of claim 33 wherein software is provided to adjust the threshold of the variable threshold transistors.

35. The mixed signal circuit of claim 33 wherein software is provided to form reconfigurable logic gate array circuit units.

36. The mixed signal circuit of claim 33 wherein software is provided to complete certain network connections among various units in the single diagram.

37. The mixed signal circuit of claim 33 wherein the software includes state tables, virtual machines, setup or initialization and test procedures, data access, transport, and storage algorithms.

38. The mixed signal circuit of claim 33 wherein the circuit is hardware driven, wherein the memory comprises hardwired Schottky CMOS Logic (SCL) gate array and memory units, IO transceivers, and terminators.

39. The mixed signal circuit of claim 38 wherein the hardware comprises software driven SCL gate arrays, IO transceivers, terminators, capacitors and wherein a switch transistor is of VT type.

40. The mixed signal circuit of claim 38 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit act as analog signal comparator.

41. The mixed signal circuit of claim 38 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL gate may perform a nonvolatile latch function.

42. The mixed signal circuit of claim 38 which includes software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of VT type, and the SCL unit may process multi-value logic operation with binary, ternary and quaternary operators.

43. The mixed signal circuit of claim 38 which includes software driven CMOS-TTL gate arrays, IO transceivers, terminators and capacitors.