System for controlling switch transistor performance

• US 20060044043A1
• Filed: 08/24/2004
• Published: 03/02/2006
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Marshall, Andrew
• Granted Patent: US 7,319,357 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H03K 17/163 Soft switching
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch transistor has a first terminal coupled to a first supply voltage (102), a second terminal coupled to an internal voltage rail (108), a gate coupled to an activation signal source (110), and a body coupled to a bias signal source (114). A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source when that transistor is shut off. A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on. A bias signal, sufficient to induce a positive body bias across the switch transistor, is applied by the bias signal source after the period of time.

Claims

1. A method for controlling performance of a switch transistor, the method comprising the steps of:

providing a switch transistor, having a first terminal coupled to a first supply voltage, a second terminal coupled to an internal voltage rail, a gate coupled to an activation signal source, and a body coupled to a bias signal source;

providing a bias signal sufficient to induce a negative body bias across the switch transistor when that transistor is shut off;

providing a bias signal sufficient to induce a negative body bias across the switch transistor for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on; and

providing a bias signal sufficient to induce a positive body bias across the switch transistor after the period of time.

2. The method of claim 1, wherein the step of providing a switch transistor further comprises providing a PMOS switch transistor, having its source coupled to the first supply voltage and its drain coupled to the internal voltage rail.

3. The method of claim 1, wherein the step of providing a switch transistor further comprises providing an NMOS switch transistor, having its drain coupled to the first supply voltage and its source coupled to the internal voltage rail.

4. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a negative body bias across the switch transistor when that transistor is shut off further comprises providing a bias signal having a magnitude greater than the first supply voltage.

5. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a negative body bias across the switch transistor for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on further comprises providing a bias signal having a magnitude greater than the first supply voltage.

6. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a negative body bias across the switch transistor for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on further comprises providing a bias signal having a magnitude greater than the bias signal sufficient to induce a negative body bias across the switch transistor when that transistor is shut off.

7. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a positive body bias across the switch transistor after the period of time further comprises providing a bias signal having a magnitude equal to the first supply voltage.

8. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a positive body bias across the switch transistor after the period of time further comprises providing a bias signal having a magnitude less than the first supply voltage.

9. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a positive body bias across the switch transistor after the period of time further comprises providing a bias signal of zero volts.

10. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a negative body bias across the switch transistor for a period of time further comprises providing a bias signal sufficient to induce a negative body bias across the switch transistor for a period of time sufficient to ensure a stable transition of the internal voltage rail.

11. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a positive body bias across the switch transistor after the period of time occurs immediately after the period of time.

12. The method of claim 1, wherein the step of providing a bias signal sufficient to induce a positive body bias across the transistor after the period of time occurs after a delay interval immediately following the period of time.

13. A semiconductor circuitry segment comprising:

a switch transistor, having a first terminal coupled to a first supply voltage, a second terminal coupled to an internal voltage rail, a gate coupled to an activation signal source, and a body coupled to a bias signal source;

wherein

the segment is adapted to induce a negative body bias across the switch transistor when the switch transistor is shut off;

the segment is adapted to induce a negative body bias across the transistor for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on; and

the segment is adapted to induce a positive body bias across the transistor after the period of time.

14. The circuitry segment of claim 13, wherein the switch transistor further comprises a PMOS switch transistor, having its source coupled to the first supply voltage and its drain coupled to the internal voltage rail.

15. The circuitry segment of claim 13, wherein the switch transistor further comprises an NMOS switch transistor, having its drain coupled to the first supply voltage and its source coupled to the internal voltage rail.

16. The circuitry segment of claim 13, wherein negative body bias across the switch transistor for a period of time following assertion of an activation signal is induced by a bias signal source having a magnitude greater than the first supply voltage.

17. The circuitry segment of claim 13, wherein negative body bias across the switch transistor for a period of time following assertion of an activation signal is induced by a bias signal having a magnitude greater than the bias signal sufficient to induce a negative body bias across the switch transistor when that transistor is shut off.

18. The circuitry segment of claim 13, wherein the positive body bias across the switch transistor is induced by a bias signal having a magnitude less than the first supply voltage.

19. The circuitry segment of claim 13, wherein the positive body bias across the switch transistor is induced by a bias signal of zero volts.