Die anti-tampering sensor

• US 20060044138A1
• Filed: 08/26/2004
• Published: 03/02/2006
• Est. Priority Date: 08/26/2004
• Status: Active Grant

• Current Assignee: Karmic Design-USA, LLC
• Original Assignee: FTD Solutions Pte., Ltd.
• Inventors: Sin, Lim Eng
• Granted Patent: US 7,119,703 B2
• Time in Patent Office: Days
• US Class Current: 340/568.200
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This sensor circuit and method for defending against tampering with an integrated circuit die uses metal wire loops to protect the circuitry. In addition, these metal wire loops have several via pairs along its length. One of the vias of the via pair goes to a NAND gate which detects a break in a section of a metal wire loop. A second via of the via pair is used to periodically discharge a metal wire loop to remove residual charge, in preparation for charging the metal wire loop and detecting any uncharged section. A given integrated circuit can have one or more metal wire loops on top of the circuitry to be protected. Each metal wire loop has one or more NAND gates. These outputs of the NAND gates can be fed into OR gates to produce an overall signal which activates an alarm or other security action such as erasure of electrically erasable programmable read only memory (EEPROM).

Claims

1. A die anti-tampering sensor for protecting against tampering of integrated circuits comprising:

a metal wire loop located in a metallization layer above said integrated circuits,

a semiconductor load device which charges said metal wire loop to a logical ‘

1’

level,

a multiplicity of semiconductor devices which discharge said metal wire loop to a logical ‘

0’

level at certain periodic times,

a NAND logic gate, with logic inputs, placed among said integrated circuits,

a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit,

a multiplicity of vias connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘

0’

level at certain periodic times, and

an output of said NAND logic gate which goes to a logic ‘

1’ and

activates an alarm and security action whenever any one of said NAND inputs goes to logical ‘

0’

.

2. The die anti-tampering sensor of claim 1 wherein said metal wire loop is placed over circuitry and memory to be protected.

3. The die anti-tampering sensor of claim 2 wherein said metal wire length has a loop which is long enough to loop across over said circuitry and memory leaving limited spaces between adjacent metal pieces.

4. The die anti-tampering sensor of claim 3 wherein said limited spaces between said adjacent metal pieces of said loop are decreased or increased to satisfy a given security requirement.

5. The die anti-tampering sensor of claim 3 wherein said wire loop has a multiplicity of via pairs distributed across said length of said wire loop.

6. The die anti-tampering sensor of claim 5 wherein said via pairs have a 1^st via to connect the metal wire loop to one of a multiplicity of said logic inputs of said NAND logic gate.

7. The die anti-tampering sensor of claim 5 wherein said via pairs have a 2^nd via to connect the metal wire loop to one of a multiplicity of said semiconductor devices which discharge said metal wire loop to a logical ‘

0’

level, at certain periodic times.

8. The die anti-tampering sensor of claim 6 wherein said 1^st via of said via pairs which connects the metal wire loop to said logic inputs of said NAND logic gates in order to detect an inability of ‘

0’

to ‘

1’

transition which signifies a break or interruption of the metal wire loop.

9. The die anti-tampering sensor of claim 8 wherein said 2^nd via of said via pairs which connects the metal wire loop to said semiconductor devices which discharge said metal wire loop to said logical ‘

0’

level in order to remove residual charge which could lead to undetected interruption of the metal wire loop.

10. The die anti-tampering sensor of claim 1 wherein said semiconductor devices which discharge said metal wire loop to logical ‘

0’

by a control clock signal.

11. The die anti-tampering sensor of claim 10 wherein said control clock signal has a ‘

1’

level to allow said discharging said metal wire loop to logical ‘

0’ and

wherein said control clock signal has a ‘

0’

level to allow said metal wire loop to charge up to a logical ‘

1’

which allows sensing of a break in said metal wire loop.

12. The die anti-tampering sensor of claim 10 wherein said semiconductor device which discharges said metal wire loop is an N-channel metal oxide field effect transistor NMOS FET whose source is connected to ground, whose gate is connected to said control clock signal, and whose drain is connected to said second via which connects to the metal wire loop.

13. The die anti-tampering sensor of claim 12 wherein said semiconductor load device which charges said metal wire loop to a logical ‘

1’

level whenever the control clock signal is at a logical ‘

0’

level.

14. The die anti-tampering sensor of claim 13 wherein said semiconductor load device is a p-channel metal oxide field effect transistor PMOS FET whose source is connected to a power supply and whose gate is connected to clock control signal and the drain is connected to said drain of said NMOS FET.

15. The die anti-tampering sensor of claim 1 wherein said NAND logic gate has an output which goes to a logical ‘

1’

whenever any NAND gate inputs go to a logical ‘

0’

wherein said NAND logical ‘

1’

output activates a security alarm or a security action such as automatic erase of electrically erasable programmable read only memory (EEPROM).

16. The die anti-tampering sensor of claim 1 wherein said metal wire loop could made from other conductive material such as polysilicon.

17. The die anti-tampering sensor of claim 1 wherein said integrated circuits have multiple metal wire loops protecting separate circuit and memory areas.

18. The die anti-tampering sensor of claim 14 wherein said PMOS FET and said NMOS FETs form a dynamic, low power circuit which dissipates AC power only.

19. The die anti-tampering sensor of claim 1 wherein outputs of multiple NAND gates go to OR circuits to develop a composite security alarm signal.

20. The die anti-tampering sensor of claim 1 wherein separate isolated multiple metal wire loops protect separate sections of circuits.

21. A method of protecting against tampering of integrated circuits comprising the steps of:

locating a metal wire loop in a metallization layer above said integrated circuits,

charging said metal wire loop to a logical ‘

1’

level with a semiconductor load device,

discharging said metal wire loop to a logical ‘

0’

level at certain periodic times with a multiplicity of semiconductor devices,

placing a NAND logic gate, with logic inputs, among said integrated circuits,

connecting a multiplicity of points along said metal wire loop down to said inputs of said NAND logic gate within said integrated circuit with a multiplicity of vias,

connecting a multiplicity of points along said metal wire loop down to said semiconductor devices which discharge said metal wire loop to a logical ‘

0’

level at certain periodic times with a multiplicity of vias, and

activating an alarm and security action whenever any one of said NAND inputs goes to logical ‘

0’

causing the output of said NAND logic gate go to a logic ‘

1’

.

22. The method of protecting against tampering of integrated circuits of claim 21 wherein said metal wire loop is placed over circuitry and memory to be protected.

23. The method of protecting against tampering of integrated circuits of claim 22 wherein said metal wire length has a loop which is long enough to loop across over said circuitry and memory leaving limited spaces between adjacent metal pieces.

24. The method of protecting against tampering of integrated circuits of claim 23 wherein said limited spaces between said adjacent metal pieces of said loop are decreased or increased to satisfy a given security requirement.

25. The method of protecting against tampering of integrated circuits of claim 23 wherein said wire loop has a multiplicity of via pairs distributed across said length of said wire loop.

26. The method of protecting against tampering of integrated circuits of claim 25 wherein said via pairs have a 1^st via to connect the metal wire loop to one of a multiplicity of said logic inputs of said NAND logic gate.

27. The method of protecting against tampering of integrated circuits of claim 25 wherein said via pairs have a 2^nd via to connect the metal wire loop to one of a multiplicity of said semiconductor devices which discharge said metal wire loop to a logical ‘

0’

level, at certain periodic times.

28. The method of protecting against tampering of integrated circuits of claim 26 wherein said 1^st via of said via pairs which connects the metal wire loop to said logic inputs of said NAND logic gates in order to detect inability of logical ‘

0’

to logical ‘

1’

transition which signifies a break or interruption of the metal wire loop.

29. The method of protecting against tampering of integrated circuits of claim 28 wherein said 2^nd via of said via pairs which connects the metal wire loop to said semiconductor devices which discharge said metal wire loop to said logical ‘

0’

level in order to remove residual charge which could lead to undetected interruption of the metal wire loop.

30. The method of protecting against tampering of integrated circuits of claim 21 wherein said semiconductor devices which discharge said metal wire loop to logical ‘

0’

by a control clock signal.

31. The method of protecting against tampering of integrated circuits of claim 30 wherein said control clock signal has a ‘

1’

level to allow said discharging said metal wire loop to logical ‘

0’ and

wherein said control clock signal has a ‘

0’

level to allow said metal wire loop to charge up to a logical ‘

1’

which allows sensing of a break in said metal wire loop.

32. The method of protecting against tampering of integrated circuits of claim 30 wherein said semiconductor device which discharges said metal wire loop is an N-channel metal oxide field effect transistor NMOS FET whose source is connected to ground, whose gate is connected to said control clock signal, and whose drain is connected to said second via which connects to the metal wire loop.

33. The method of protecting against tampering of integrated circuits of claim 32 wherein said semiconductor load device which charges said metal wire loop to a logical ‘

1’

level whenever the control clock signal is at a logical ‘

0’

level.

34. The method of protecting against tampering of integrated circuits of claim 33 wherein said semiconductor load device is a p-channel metal oxide field effect transistor PMOS FET whose source is connected to a power supply and whose gate is connected to clock control signal and the drain is connected to said drain of said NMOS FET.

35. The method of protecting against tampering of integrated circuits of claim 21 wherein said NAND logic gate has an output which goes to a logical ‘

1’

whenever any NAND gate inputs go to a logical ‘

0’

wherein said NAND logical ‘

1’

output activates a security alarm or a security action such as automatic erase of electrically erasable programmable read only memory (EEPROM).

36. The method of protecting against tampering of integrated circuits of claim 21 wherein said metal wire loop could made from other conductive material such as polysilicon.

37. The method of protecting against tampering of integrated circuits of claim 21 wherein said integrated circuits have multiple metal wire loops protecting separate circuit and memory areas.

38. The method of protecting against tampering of integrated circuits of claim 34 wherein said PMOS FET and said NMOS FETs form a dynamic, low power circuit which dissipates AC power only.

39. The method of protecting against tampering of integrated circuits of claim 21 wherein outputs of multiple NAND gates go to OR circuits to develop a composite security alarm signal.

40. The method of protecting against tampering of integrated circuits of claim 21 wherein separate isolated multiple metal wire loops protect separate sections of circuits.