High dynamic range imager with a rolling shutter

• US 20060044413A1
• Filed: 08/27/2004
• Published: 03/02/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Krymski, Alexander
• Granted Patent: US 7,397,509 B2
• Time in Patent Office: Days
• US Class Current: 348/230.100
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures

Abstract

A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the imager are adapted to process pixel signals corresponding to the integration periods in parallel. The pixel signals are converted into digital values in parallel. The digital values are each linear functions of the incident light and therefore suitable for use with conventional color processing algorithms. A pipelined rolling shutter operation may be employed where the short integration period of one row of pixels is performed simultaneously with the long integration period of another row of pixels.

Claims

1. A pixel reading circuit, comprising:

a signal input node for receiving a reset signal, a first photo signal, and a second photo signal;

a first sample and hold circuit coupled to a signal input node;

a second sample and hold circuit coupled to said signal input node;

a third sample and hold circuit coupled to said signal input node;

a first output circuit, coupled to receive signals from said first and second sample and hold circuits; and

a second output circuit, coupled to receive signals from said first and third sample and hold circuits.

2. The pixel reading circuit of claim 1, further comprising a bias circuit, coupled to said signal input node.

3. The pixel reading circuit of claim 2, wherein said bias circuit and said first, second, and third sample and hold circuits are coupled in parallel to said signal input node.

4. The pixel reading circuit of claim 1, wherein said first and second output circuit each comprise a differential amplifier.

5. The pixel reading circuit of claim 1, wherein said first photo signal is associated with a first integration period of said pixel and said second photo signal is associated with a second integration period of said pixel.

6. The pixel reading circuit of claim 5, wherein said second integration period is longer than said first integration period.

7. An imager, comprising:

a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns;

a plurality of pixel reading circuits, each of said pixel reading circuits comprising;

a first, second, and third sample and hold circuits, for respectively sampling and holding a reset signal, a first photo signal, and a second photo signal, from one of said plurality of pixels;

a first output circuit for producing a first pixel signal from said reset signal and said first photo signal; and

a second output circuit for producing a second pixel signal from said reset signal and said second photo signal;

a first analog to digital converter, coupled to said first output circuit, for producing a first digital value corresponding to said first pixel signal; and

a second analog to digital converter, coupled to said second output circuit, for producing a second digital value corresponding to said second pixel signal.

8. The imager of claim 7, further comprising:

an image processor coupled to said first and second analog to digital converters, said image processor receiving said first and second digital values;

wherein said image processor

calculates a first intermediate result by performing linear arithmetic operations on said first digital value,

calculates a second intermediate result by performing linear arithmetic operations on said second digital value, and

calculates a next result by performing arithmetic operations on said first and second intermediate results.

9. The imager of claim 8, wherein said image processor performs color processing upon at least one of said first and second digital values.

10. The imager of claim 7, further comprising a controller coupled to said pixel array and said plurality of pixel reading circuits, wherein said controller operates said plurality of pixels over a short integration period and a long integration period.

11. The imager of claim 10, wherein said first photo signal is associated with said short integration period and said second photo signal is associated with said long integration period.

12. A system, comprising:

a processor;

an imager coupled to said processor, said imager comprising;

a pixel array comprising a plurality of pixels arranged in a plurality of rows and a plurality of columns;

a plurality of pixel reading circuits, each of said pixel reading circuits comprising;

a first, second, and third sample and hold circuits, for respectively sampling and holding a reset signal, a first photo signal, and a second photo signal, from one of said plurality of pixels;

a first output circuit for producing a first pixel signal from said reset signal and said first photo signal; and

a second output circuit for producing a second pixel signal from said reset signal and said second photo signal;

a first analog to digital converter, coupled to said first output circuit, for producing a first digital value corresponding to said first pixel signal; and

a second analog to digital converter, coupled to said second output circuit, for producing a second digital value corresponding to said second pixel signal.

13. The imager of claim 12, further comprising:

an image processor coupled to said first and second analog to digital converters, said image processor receiving said first and second digital values;

wherein said image processor

calculates a first intermediate result by performing linear arithmetic operations on said first digital value,

calculates a second intermediate result by performing linear arithmetic operations on said second digital value, and

calculates a next result by performing arithmetic operations on said first and second intermediate results..

14. The imager of claim 13, wherein said image processor performs color processing upon at least one of said first and second digital values.

15. The imager of claim 12, further comprising a controller coupled to said pixel array and said plurality of pixel reading circuits, wherein said controller operates said plurality of pixels over a short integration period and a long integration period.

16. The imager of claim 15, wherein said first photo signal is associated with said short integration period and said second photo signal is associated with said long integration period.

17. A method for reading a pixel, comprising:

(a) sampling and holding a first photo signal from said pixel;

(b) sampling and holding a reset signal from said pixel;

(c) sampling and holding a second photo signal from said pixel;

(d) forming a first output signal from said first photo signal and said reset signal; and

(e) forming a second output signal from said second photo signal and said reset signal.

18. The method of claim 17, wherein step (b) is performed between step (a) and step (b).

19. The method of claim 18, wherein step (d) is performed after step (a) and step (b).

20. The method of claim 18, wherein step (e) is performed after step (b) and step (c).

21. The method of claim 17, wherein step (d) and step (e) overlap in time.

22. The method of claim 17, wherein step (d) and step (e) are performed at a same time.

23. The method of claim 17, further comprising:

(f) digitizing said first output signal to produce a first digital value; and

(g) digitizing said second output signal to produce a second digital value.

24. The method of claim 23, wherein step (f) and step (g) overlap in time.

25. The method of claim 23, wherein step (f) and step (g) are performed at a same time.

34. The method of claim 23, further comprising:

(h) after steps (f) and (g), performing linear arithmetic operations on said first and second digital values to respectively obtain a first and second intermediate results; and

(i) after step (h), performing arithmetic operations on said first and second intermediate results.

26. A method of operating an imager, comprising:

(a) selecting a first row from a plurality of rows, each comprising a plurality of pixels, of a pixel array;

(b) resetting each pixel in said first row to start a first integration period;

(c) in each pixel of said first row, starting a first temporary transfer of charge accumulated during said first integration period to a charge accumulation node, and starting a second integration period at the end of said first temporary transfer;

(d) in each pixel of said first row, outputting a first photo signal associated with said first integration period;

(e) resetting each pixel in said first row to output a first reset signal;

(f) in each pixel of said first row, outputting a second photo signal associated with said second integration period.

27. The method of claim 26, further comprising:

in each pixel of said first row,

forming a first pixel signal from said first photo signal and said first reset signal; and

forming a second pixel signal from said second photo signal and said first reset signal.

28. The method of claim 27, further comprising:

in each pixel of said first row,

forming a first digital value by digitizing said first pixel signal; and

forming a second digital value by digitizing said second pixel signal.

29. The method of claim 26, wherein said second integration period is longer than said first integration period.

30. The method of claim 26, further comprising:

(g) selecting a second row from said plurality of rows;

(h) resetting each pixel in said second row to start a third integration period;

(i) in each pixel of said second row, starting a second temporary transfer of charge accumulated during said third integration period to a charge accumulation node, and starting a fourth integration period at the end of said second temporary transfer;

(j) in each pixel of said second row, outputting a third photo signal associated with said third integration period;

(k) resetting each pixel in said second row to output a second reset signal;

(l) in each pixel of said second row, outputting a fourth photo signal associated with said fourth integration period.

31. The method of claim 30, wherein steps (g), (h), and (i) are performed after steps (a), (b), and (c).

32. The method of claim 31, wherein steps (d), (e), and (f) are performed after steps (g), (h), and (i).

33. The method of claim 32, wherein steps 0), (k), and (1) are performed after steps (d), (e), and (f).