Host interface for imaging arrays

• US 20060044435A1
• Filed: 10/27/2005
• Published: 03/02/2006
• Est. Priority Date: 01/21/2000
• Status: Active Grant

• Current Assignee: Cedar Lane Technologies Inc.
• Original Assignee: Harusaki Technologies LLC (Transpacific IP Group Limited)
• Inventors: Suska, Mark
• Granted Patent: US 8,537,242 B2
• Time in Patent Office: Days
• US Class Current: 348/294
• CPC Class Codes: H04N 23/72 Combination of two or more compensation controls
• CPC Class Codes: H04N 23/74 by influencing the scene brightness using illuminating means
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system.

Claims

1-23. -23. (canceled)

24. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus and a system address/control bus comprising:

an imaging array of sensing pixels;

a buffer for storing data received at an input port and for outputting data through an output port to the data bus;

a unit for transferring data from a selected pixel to the buffer input port;

a counter for determining the quantity of data in the buffer;

a signal generator for seeking control of the data bus when the quantity of data in the buffer attains a predetermined level; and

a circuit adapted to respond to the availability of the data bus for controlling the transfer of the stored data through the buffer output port.

25. An integrated semiconductor imaging circuit as claimed in claim 24 which includes a bus arbitration unit for receiving data bus control requests and for providing data bus control in response to a request.

26. An integrated semiconductor imaging circuit as claimed in claim 25 wherein the circuit for responding to the availability of the data bus includes:

an address unit for storing and incrementing destination addresses; and

a bus command unit for asserting the destination address and write controls on the system address/control bus.

27. (canceled)

28. An integrated semiconductor imaging circuit for use with an electronic processing system having a data bus and a system address/control bus comprising:

an imaging array of sensing pixels;

memory having a plurality of memory cells arranged in rows and columns for storing data received at an input port and for outputting data through an output port to the data bus;

a unit for transferring data from a selected pixel to a selected memory cell through the memory input port;

a counter for determining the quantity of data in the memory;

a signal generator for seeking control of the data bus when the quantity of data in the memory attains a predetermined level; and

a circuit adapted to respond to the availability of the data bus for controlling the transfer of the stored data through the memory output port.

29. An integrated semiconductor imaging circuit as claimed in claim 28 which includes a bus arbitration unit for receiving data bus control requests and for providing data bus control in response to a request.

30. An integrated semiconductor imaging circuit as claimed in claim 29 wherein the circuit for responding to the availability of the data bus includes:

an address unit for storing and incrementing destination addresses; and

a bus command unit for asserting the destination address and write controls on the system address/control bus.