MEMORY STACKING SYSTEM AND METHOD
First Claim
1. A method of forming a stacked memory module, comprising:
- providing a plurality of memory devices to include a logic block for decoding a plurality of chip select signals;
stacking the plurality of memory devices;
interconnecting a plurality of pins between the plurality of memory devices, including a chip select pin and a first unused pin of each of the plurality of memory devices; and
updating a serial presence detect device to indicate the stacked memory module includes the plurality of memory devices and each of the plurality of chip select signals is transmitted to a corresponding one of a plurality of designated pins on the plurality of memory devices.
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Accused Products
Abstract
A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.
56 Citations
32 Claims
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1. A method of forming a stacked memory module, comprising:
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providing a plurality of memory devices to include a logic block for decoding a plurality of chip select signals;
stacking the plurality of memory devices;
interconnecting a plurality of pins between the plurality of memory devices, including a chip select pin and a first unused pin of each of the plurality of memory devices; and
updating a serial presence detect device to indicate the stacked memory module includes the plurality of memory devices and each of the plurality of chip select signals is transmitted to a corresponding one of a plurality of designated pins on the plurality of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A high density memory module, comprising:
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a plurality of memory devices, each comprising logic to decode a binary combination of a plurality of chip select signals received on a plurality of designated pins; and
a serial presence detect device configured to indicate to a memory controller a number of chip select signals to be sent to the plurality of memory devices, and configured to encode the plurality of chip select signals. - View Dependent Claims (12, 13, 14, 15)
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16. An electronic system, comprising:
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an input device;
an output device;
a memory system, comprising a memory controller; and
a processor device coupled to the input device, the output device and the memory system, at least one of the input device, the output device, the memory system and the processor device including a high density memory module comprising;
a plurality of memory devices, each comprising logic to decode a binary combination of a plurality of chip select signals received on a plurality of designated pins; and
a serial presence detect device configured to indicate to a memory controller a number of chip select signals to be sent to the plurality of memory devices, and configured to encode the plurality of chip select signals. - View Dependent Claims (17, 18, 19, 20)
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21. A method of forming a stacked memory module, comprising:
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configuring an address buffer to include a logic block for decoding a plurality of chip select signals, the address buffer further connected to a plurality of memory devices;
stacking the plurality of memory devices to interconnect a plurality of pins, wherein a chip select pin of each of the plurality of memory devices is exclusively connected to the address buffer; and
updating a serial presence detect device to indicate that the stacked memory module includes the plurality of memory devices and that each of the plurality of chip select signals is transmitted to the address buffer. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A high density memory module comprising:
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a plurality of memory devices, each comprising a chip select pin;
an address buffer, comprising a logic block to decode a binary combination of chip select signals; and
a serial presence detect device capable of indicating to a memory controller a number of chip select signals to be sent to the plurality of memory devices, a manner of encoding the chip select signals, and a designation of traces on which the chip select signals are to be sent. - View Dependent Claims (28, 29)
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30. An electronic system, comprising:
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an input device;
an output device;
a memory system, comprising a memory controller; and
a processor device coupled to the input device, the output device and the memory system, at least one of the input device, the output device, the memory system and the processor device including a high density memory module comprising;
a plurality of memory devices, each comprising a chip select pin;
an address buffer, comprising a logic block to decode a binary combination of chip select signals; and
a serial presence detect device configured to indicate to a memory controller a number of chip select signals to be sent to the plurality of memory devices, and configured to encode the chip select signals. - View Dependent Claims (31, 32)
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Specification