Semiconductor integrated circuit

• US 20060044871A1
• Filed: 08/03/2005
• Published: 03/02/2006
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tanaka, Toshihiro, Yamaki, Takashi, Shinagawa, Yutaka, Tanikawa, Hiroyuki
• Granted Patent: US 7,286,410 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

Claims

1. A semiconductor integrated circuit comprising:

a central processing unit; and

a rewritable nonvolatile memory area provided in an address space in the central processing unit,

wherein the nonvolatile memory area includes a first nonvolatile memory area and a second nonvolatile memory area, each of which is capable of storing information in accordance with the difference in threshold voltages,

wherein one or plural conditions out of erase verify voltage, erase verify current, write verify voltage, write verify current, erase voltage, erase voltage application time, write voltage, and write voltage application time is/are made different between the first nonvolatile memory area and the second nonvolatile memory area,

wherein speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and

wherein the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

2. The semiconductor integrated circuit according to claim 1,

wherein when an erase verify voltage in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the erase verify voltage in the first nonvolatile memory area is set to be lower than that in the second nonvolatile memory area.

3. The semiconductor integrated circuit according to claim 1,

wherein when an erase verify current in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the erase verify current in the first nonvolatile memory area is set to be larger than that in the second nonvolatile memory area.

4. The semiconductor integrated circuit according to claim 1,

wherein when a write verify voltage in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the write verify voltage in the first nonvolatile memory area is set to be higher than that in the second nonvolatile memory area.

5. The semiconductor integrated circuit according to claim 1,

wherein when a write verify current in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the write verify current in the first nonvolatile memory area is set to be smaller than that in the second nonvolatile memory area.

6. The semiconductor integrated circuit according to claim 1,

wherein when a write verify voltage and an erase verify current in the first nonvolatile memory area are different from those in the second nonvolatile memory area, the write verify current in the first nonvolatile memory area is set to be higher than that in the second nonvolatile memory area, and the erase verify voltage in the first nonvolatile memory area is set to be lower than that in the second nonvolatile memory area.

7. The semiconductor integrated circuit according to claim 1,

wherein when an erase voltage in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the erase voltage in the first nonvolatile memory area is set to be higher than that in the second nonvolatile memory area.

8. The semiconductor integrated circuit according to claim 1,

wherein when erase voltage application time in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the erase voltage application time in the first nonvolatile memory area is set to be longer than that in the second nonvolatile memory area.

9. The semiconductor integrated circuit according to claim 1,

wherein when a write voltage in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the write voltage in the first nonvolatile memory area is set to be higher than that in the second nonvolatile memory area.

10. The semiconductor integrated circuit according to claim 1,

wherein when write voltage application time in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the write voltage application time in the first nonvolatile memory area is set to be longer than that in the second nonvolatile memory area.

11. The semiconductor integrated circuit according to claim 1,

wherein memory cell gate length and/or memory cell gate width in the first nonvolatile memory area are/is different from those/that in the second nonvolatile memory area.

12. The semiconductor integrated circuit according to claim 11,

wherein when a memory cell gate length in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the memory cell gate length in the first nonvolatile memory area is set to be shorter than that in the second nonvolatile memory area.

13. The semiconductor integrated circuit according to claim 12,

wherein when a memory cell gate width in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the memory cell gate width in the first nonvolatile memory area is set to be larger than that in the second nonvolatile memory area.

14. The semiconductor integrated circuit according to claim 1,

wherein the first nonvolatile memory having the first nonvolatile memory area, and the second nonvolatile memory having the second nonvolatile memory area are separately provided.

15. The semiconductor integrated circuit according to claim 1,

wherein a single nonvolatile memory having both of the first and second nonvolatile memory areas is provided.

16. The semiconductor integrated circuit according to claim 1,

wherein the first nonvolatile memory area is used for storing a program, and the second nonvolatile memory area is used for storing data.

17. A semiconductor integrated circuit comprising:

a central processing unit; and

a rewritable nonvolatile memory area provided in an address space in the central processing unit,

wherein the nonvolatile memory area includes a first nonvolatile memory area and a second nonvolatile memory area, each of which is capable of storing information in accordance with the difference in threshold voltages,

wherein memory cell gate length and/or memory cell gate width in the first nonvolatile memory area are/is different from those/that in the second nonvolatile memory area,

wherein speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and

wherein the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

18. The semiconductor integrated circuit according to claim 17,

wherein when memory cell gate length in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the memory cell gate length in the first nonvolatile memory area is set to be shorter than that in the second nonvolatile memory area.

19. The semiconductor integrated circuit according to claim 17,

wherein when memory cell gate width in the first nonvolatile memory area is different from that in the second nonvolatile memory area, the memory cell gate width in the first nonvolatile memory area is set to be larger than that in the second nonvolatile memory area.

20. A data processing method of rewriting a first nonvolatile memory area and a second nonvolatile memory area, each of which is capable of storing information in accordance with the difference in threshold voltages, in a data processing system comprising the first and second nonvolatile memory areas and a central processing unit capable of accessing the first and second memory areas, comprising the steps of:

making one or plural conditions out of erase verify voltage, erase verify current, write verify voltage, write verify current, erase voltage, erase voltage application time, write voltage, and write voltage application time different between the first nonvolatile memory area and the second nonvolatile memory area;

setting speed of reading information stored in the first nonvolatile memory area to be higher than that of reading information stored in the second nonvolatile memory area; and

setting the assured number of rewriting times in the second nonvolatile memory area to be larger than that in the first nonvolatile memory area.