Multiple-level data compression read more for memory testing
First Claim
1. A data compression circuit in a memory device, comprising:
- a plurality of first level data compression circuits for receiving data signals corresponding to bit locations of each word of a group of words of the memory device and for providing a first match signal and a second match signal, the first match signal having a first logic level and the second match signal having a second logic level if a corresponding bit location for each word of the group has a first data value, the first match signal having the second logic level and the second match signal having the first logic level if the corresponding bit location for each word of the group has a second data value, and the first and second match signals otherwise having the same logic level; and
a second level data compression for receiving the first and second match signals from each of the first level data compression circuits and for providing a third match signal having a first logic level if all of the first match signals have the same logic level and all of the second match signals have the same logic level, and otherwise having a second logic level.
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Abstract
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.
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Citations
42 Claims
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1. A data compression circuit in a memory device, comprising:
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a plurality of first level data compression circuits for receiving data signals corresponding to bit locations of each word of a group of words of the memory device and for providing a first match signal and a second match signal, the first match signal having a first logic level and the second match signal having a second logic level if a corresponding bit location for each word of the group has a first data value, the first match signal having the second logic level and the second match signal having the first logic level if the corresponding bit location for each word of the group has a second data value, and the first and second match signals otherwise having the same logic level; and
a second level data compression for receiving the first and second match signals from each of the first level data compression circuits and for providing a third match signal having a first logic level if all of the first match signals have the same logic level and all of the second match signals have the same logic level, and otherwise having a second logic level. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A data compression circuit in a memory device, comprising:
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for each word of a group of words of the memory device;
a first logic circuit for receiving data signals corresponding to a given bit location of each word of a group of words and for providing a first output signal indicative of whether each data signal has a first data value;
a second logic circuit for receiving the data signals corresponding to the given bit location of each word of that group of words of the memory device and for providing a second output signal indicative of whether each data signal has a second data value;
for each group of words of a plurality of words of the memory device;
a third logic circuit for receiving each of the first and second match signals corresponding to a group of words and for providing a first match signal and a second match signal, the first match signal having a first logic level and the second match signal having a second logic level when the first output signal indicates that each data signal has its first data value, the first match signal having the second logic level and the second match signal having the first logic level when the second output signal indicates that each data signal has its second data value, and the first and second match signals having the same logic level when the first match signal does not indicate that each data signal has its first data value and the second match signal does not indicate that each data signal has its second data value;
a fourth logic circuit for receiving the first match signals for each of the groups of words and for providing a third output signal indicative of whether each first match signal has its second logic level;
a fifth logic circuit for receiving the first match signals for each of the groups of words and for providing a fourth output signal indicative of whether each first match signal has its first logic level;
a sixth logic circuit for receiving the second match signals for each of the groups of words and for providing a fifth output signal indicative of whether each second match signal has its second logic level;
a seventh logic circuit for receiving the second match signals for each of the groups of words and for providing a sixth output signal indicative of whether each second match signal has its first logic level;
an eighth logic circuit for receiving each of the third, fourth, fifth and sixth output signals and for providing a third match signal having a first logic level if each of the third and fourth output signals have the same logic level and each of the fifth and sixth output signals have the same logic level. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A memory device, comprising:
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a plurality of first level data compression circuits for receiving data signals corresponding to bit locations of each word of a group of words of the memory device and for providing a first match signal and a second match signal, the first match signal having a first logic level and the second match signal having a second logic level if a corresponding bit location for each word of the group has a first data value, the first match signal having the second logic level and the second match signal having the first logic level if the corresponding bit location for each word of the group has a second data value, and the first and second match signals otherwise having the same logic level;
a second level data compression for receiving the first and second match signals from each of the first level data compression circuits and for providing a third match signal having a first logic level if all of the first match signals have the same logic level and all of the second match signals have the same logic level, and otherwise having a second logic level; and
an output driver circuit for providing an output signal indicative of a data signal, wherein the output driver circuit is disabled when the third match signal has its first logic level. - View Dependent Claims (32, 33, 34)
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35. A method of testing a memory device, comprising:
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accessing a memory array of the memory device to generate data signals for two or more groups of words, each group of words comprising two or more words, each word comprising two or more bit locations;
comparing data signals for a given bit location of each word of a group of words for the two or more groups of words;
generating a first match signal and a second match signal for each group of words in response to the comparison of the data signals, each set of first and second match signals having a first logic level when each of the data signals for a given bit location has a first data value for each word of that group of words, each set of first and second match signals having a second logic level when each of the data signals for a given bit location has a second data value for each word of that group of words, and otherwise each set of first and second match signals having differing logic levels for that group of words;
comparing each of the first match signals and comparing each of the second match signals;
generating a third match signal in response to the comparison of the first match signals and the comparison of the second match signals, wherein the third match signal has a first logic level only when each of the first match signals has the same logic level and each of the second match signals has the same logic level;
disabling output for data signals corresponding to at least the given bit location if the third match signal has a second logic level;
attempting to read a word of the memory device; and
determining whether output is disabled for at least the given bit location, wherein disabled output is indicative of failure of the memory device. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
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Specification