Memory system and method for strobing data, command and address signals

• US 20060044891A1
• Filed: 08/31/2004
• Published: 03/02/2006
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Keeth, Brent, Johnson, Brian, Lin, Feng, Lee, Seong-hoon
• Granted Patent: US 7,126,874 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

Claims

1. A memory system for coupling a command, address or data signal between a memory controller and a memory device, comprising:

a communication path coupled between the memory controller and memory device;

a first strobe generator circuit in one of the memory controller or the memory device, the first strobe generator circuit being operable to generate a first periodic strobe signal and a second periodic strobe signal, the first strobe signal having signal transitions that are offset from signal transitions of the second strobe signal by 90 degrees;

a first output latch in the memory controller or the memory device containing the first strobe generator circuit, the first output latch having an input terminal coupled to receive the command, address or data signal, an output terminal coupled to the communications path, and a clock terminal coupled to receive the first strobe signal;

a first input latch in the memory controller or the memory device not containing the first strobe generator circuit, the first input latch having an input terminal coupled to the communications path, an output terminal, and a clock terminal; and

a first strobe signal path coupling the second strobe signal from the first strobe generator circuit to the clock terminal of the first input latch.

2. The memory system of claim 1 wherein the first strobe generator circuit and the first output latch are in the memory controller, and the first input latch is in the memory device.

3. The memory system of claim 2 wherein the communication path comprises a command bus, and wherein the command, address or data signal comprises a memory command signal.

4. The memory system of claim 2 wherein the communication path comprises an address bus, and wherein the command, address or data signal comprises a memory address signal.

5. The memory system of claim 2 wherein the communication path comprises a data bus, and wherein the command, address or data signal comprises a write data signal.

6. The memory system of claim 5, further comprising:

a second strobe generator circuit in the memory device, the second strobe generator circuit being operable to generate a third periodic strobe signal and a fourth periodic strobe signal, the third strobe signal having signal transitions that are offset from signal transitions of the fourth strobe signal by 90 degrees;

a second output latch in the memory device, the second output latch having an input terminal coupled to receive a data read signal, an output terminal coupled to the data bus, and a clock terminal coupled to receive the fourth strobe signal;

a second input latch in the memory controller, the second input latch having an input terminal coupled to the data bus, an output terminal, and a clock terminal; and

a second strobe signal path coupling the third strobe signal from the second strobe generator circuit to the clock terminal of the second input latch.

7. The memory system of claim 1 wherein the first strobe generator circuit and the first output latch are in the memory device, and the first input latch is in the memory controller.

8. The memory system of claim 6 wherein the communication path comprises a data bus, and wherein the command, address or data signal comprises a read data signal.

9. The memory system of claim 1 wherein the first strobe generator circuit generates a plurality of phases of the first strobe signal that differ from each other by N*180 degrees, and a plurality of phases of the second strobe signal that differ from each other by N*180 degrees, where N is a positive integer, and wherein:

the first output latch comprises a plurality of input terminals each receiving and storing a respective bit of a memory command, address or data;

the first output latch comprises a plurality of clock terminals each of which receives a respective one of the phases of the first strobe signal;

the first output latch is operable to couple a bit of the memory command, address or data stored in the first output latch to the output terminal of the first output latch responsive to each transition of one of the phases of the first strobe signal coupled to the clock terminals of the first output latch;

the first input latch comprises a plurality of clock terminals each of which receives a respective one of the phases of the second strobe signals through the first strobe signal path; and

the first input latch is operable to store a bit of the memory command, address or data coupled to the input terminal of the first input latch through the communication path responsive to each transition of one of the phases of the second strobe signal coupled to the clock terminals of the first input latch.

10. The memory system of claim 9 wherein the number of bits stored in the first output latch and the first input latch comprise four bits.

11. The memory system of claim 1 wherein the first strobe generator circuit comprises:

a delay-lock loop receiving an input clock signal, the delay-lock loop comprising;

a phase detector having first input terminal receiving the input clock signal and second input terminal receiving a feedback clock signal, the phase detector being operable to generate at an output terminal a phase control voltage having a magnitude corresponding to the phase difference between input clock signal and the feedback clock signal; and

a delay line having an input coupled to receive the input clock signal, the delay line outputting a delayed clock signal having a phase relative to the phase of the input clock signal that is controlled by the phase control voltage;

a phase generator circuit coupled to receive the delayed clock signal from the delay line, the phase generator circuit generating the first strobe signal and the second strobe signal from the delayed clock signal; and

a feedback path coupling the first strobe signal to the second input of the phase detector as the feedback clock signal.

12. The memory system of claim 11 wherein the phase generator circuit comprises:

a second phase detector operable to generate a delay control signal corresponding to phase difference between first and second signals coupled to respective inputs of the second phase detector; and

a plurality of delay elements sequentially coupled to each other from a first delay element to a last delay element, each of the delay elements delaying a signal coupled to its input by a delay that is controlled by the delay control signal, the delayed clock signal being coupled to the first delay element, the first delay element generating the first signal coupled to the first input of the second phase detector, and the last delay element generating the second signal coupled to the second input of the second phase detector so that the phase of the first and second signals are equal to each other and respective phases of second and first strobe signals are generated at the outputs of respective ones of the delay elements.

13. The memory system of claim 12 wherein the plurality of delay elements comprise eight delay elements generating first and second strobe signals having phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively.

14. A circuit for generating a strobe signal, comprising:

a delay-lock loop receiving an input clock signal, the delay-lock loop comprising;

a phase detector having first input terminal receiving the input clock signal and second input terminal receiving a feedback clock signal, the phase detector being operable to generate at an output terminal a phase control voltage having a magnitude corresponding to the phase difference between input clock signal and the feedback clock signal; and

a delay line having an input coupled to receive the input clock signal, the delay line outputting a delayed clock signal having a phase relative to the phase of the input clock signal that is controlled by the phase control voltage;

a phase generator circuit coupled to receive the delayed clock signal from the delay line, the phase generator circuit generating a first strobe signal and a second strobe signal from the delayed clock signal, the second strobe signal having a phase offset from the first strobe signal of 90 degrees; and

a feedback path coupling the first strobe signal to the second input of the phase detector as the feedback clock signal.

15. The strobe signal generating circuit of claim 14 wherein the phase generator circuit comprises:

a second phase detector operable to generate a delay control signal corresponding to phase difference between first and second signals coupled to respective inputs of the second phase detector; and

a plurality of delay elements coupled in series from a first delay element to a last delay element, each of the delay elements delaying a signal coupled to its input by a delay that is controlled by the delay control signal, the delayed clock signal being coupled to the first delay element, the first delay element generating the first signal coupled to the first input of the second phase detector, and the last delay element generating the second signal coupled to the second input of the second phase detector so that the phase of the first and second signals are equal to each other and respective phases of second and first strobe signals are generated at the outputs of respective ones of the delay elements.

16. The strobe signal generating circuit of claim 15 wherein the plurality of delay elements comprise eight delay elements generating second and first strobe signals having phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively.

17. A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a strobe generator circuit operable to generate a first periodic strobe signal and a second periodic strobe signal, the second strobe signal having signal transitions that are offset from signal transitions of the first strobe signal by 90 degrees, the second strobe signal being coupled to an external strobe signal output terminal of the memory device;

a data path circuit operable to couple data signals corresponding to the data between the array and data bus terminals of the memory device, the data path circuit comprising;

an output latch having an input terminal coupled to the array, an output terminal coupled to the data bus terminals, and a clock terminal coupled to receive the first strobe signal from the strobe generator circuit and to couple read data bits from the output latch to the data bus terminals responsive to a transition of the first strobe signal; and

an input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the array, and a clock terminal coupled to receive the second strobe signal from a strobe signal input terminal; and

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.

18. The memory device of claim 17 wherein the strobe generator circuit generates a plurality of phases of the first strobe signal that differ from each other by N*180 degrees, and a plurality of phases of the second strobe signal that differ from each other by N*180 degrees, where N is a positive integer, and wherein:

the output latch comprises a plurality of input terminals each receiving from the array and storing a respective bit of read data, and a plurality of clock terminals each of which receives a respective one of the phases of the first strobe signal, the output latch being operable to couple a respective stored read data bit to the output terminal of the output latch responsive to each transition of one of the phases of the first strobe signal coupled to the clock terminals of the first output latch; and

the input latch comprises a plurality of clock terminals each coupled to receive a respective phase of the second strobe signal from a respective strobe signal input terminal, the input latch being operable to store a bit of write data coupled to the data bus terminal of the memory device responsive to each transition of one of the phases of the second strobe signal coupled to the clock terminals of the input latch, the input latch having a plurality of output terminals coupling a respective bit of write data to the memory array.

19. The memory device of claim 18 wherein the number of bits stored in the output latch and the input latch comprise four bits.

20. The memory device of claim 17 wherein the strobe generator circuit comprises:

a delay-lock loop receiving an input clock signal, the delay-lock loop comprising;

a phase detector having first input terminal receiving the input clock signal and second input terminal receiving a feedback clock signal, the phase detector being operable to generate at an output terminal a phase control voltage having a magnitude corresponding to the phase difference between input clock signal and the feedback clock signal; and

a delay line having an input coupled to receive the input clock signal, the delay line outputting a delayed clock signal having a phase relative to the phase of the input clock signal that is controlled by the phase control voltage;

a phase generator circuit coupled to receive the delayed clock signal from the delay line, the phase generator circuit generating the first strobe signal and the second strobe signal from the delayed clock signal; and

a feedback path coupling the first strobe signal to the second input of the phase detector as the feedback clock signal.

21. The memory device of claim 20 wherein the phase generator circuit comprises:

a second phase detector operable to generate a delay control signal corresponding to phase difference between first and second signals coupled to respective inputs of the second phase detector; and

a plurality of delay elements sequentially coupled to each other from a first delay element to a last delay element, each of the delay elements delaying a signal coupled to its input by a delay that is controlled by the delay control signal, the delayed clock signal being coupled to the first delay element, the first delay element generating the first signal coupled to the first input of the second phase detector, and the last delay element generating the second signal coupled to the second input of the second phase detector so that the phase of the first and second signals are equal to each other and respective phases of second and first strobe signals are generated at the outputs of respective ones of the delay elements.

22. The memory device of claim 21 wherein the plurality of delay elements comprise eight delay elements generating second and first strobe signals having phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively.

23. The memory device of claim 17 wherein the memory comprises a dynamic random access memory array.

24. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus to allow data to be output from the computer system;

a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;

a memory controller coupled to the processor through the processor bus, the memory controller comprising

a first strobe generator circuit operable to generate a first strobe signal and a second strobe signal, the second strobe signal having signal transitions that are offset from signal transitions of the first strobe signal by 90 degrees, the second strobe signal being coupled to a strobe signal output terminal of the memory controller;

a data path circuit operable to couple read data signals to the processor from data bus terminals of the memory controller and to coupled write data signals to the data bus terminals of the memory controller from the processor, the data path circuit comprising;

a first output latch having an input terminal coupled to the processor, an output terminal coupled to the data bus terminals of the memory controller, and a clock terminal coupled to receive the first strobe signal from the strobe generator circuit, the first output latch being operable to couple read data bits from the output latch to the data bus terminals responsive to a transition of the first strobe signal; and

a first input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the processor, and a clock terminal coupled to a strobe signal input terminal of the memory controller; and

a memory device coupled to the memory controller, the memory device comprising;

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;

a column address circuit operable to receive and decode column address signals applied to the external address terminals;

a memory cell array operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals;

a second strobe generator circuit operable to generate a periodic third strobe signal and a periodic fourth strobe signal, the fourth strobe signal having signal transitions that are offset from signal transitions of the third strobe signal by 90 degrees, the fourth strobe signal being coupled to the strobe signal input terminal of the memory controller;

a data path circuit operable to couple data signals corresponding to the data between the array and data bus terminals of the memory device, the data path circuit comprising;

a second output latch having an input terminal coupled to the array, an output terminal coupled to the data bus terminals, and a clock terminal coupled to receive the third strobe signal from the second strobe generator circuit and to couple read data bits from the output latch to the data bus terminals responsive to a transition of the third strobe signal; and

a second input latch having an input terminal coupled to the data bus terminals, an output terminal coupled to the array, and a clock terminal coupled to receive the second strobe signal from the strobe signal output terminal of the memory controller; and

a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals.

25. The computer system of claim 24 wherein the first and second strobe generator circuits generate a plurality of phases of the first and third strobe signals, respectively, that differ from each other by N*180 degrees, and a plurality of phases of the second and fourth strobe signals, respectively, that differ from each other by N*180 degrees, where N is a positive integer, and wherein:

the first output latch comprises a plurality of input terminals each receiving from the processor and storing a respective bit of write data, and a plurality of clock terminals each of which receives a respective one of the phases of the first strobe signal generated by the first strobe generator circuit, the first output latch being operable to couple a respective stored write data bit to the output terminal of the first output latch responsive to each transition of one of the phases of the first strobe signal coupled to the clock terminals of the first output latch; and

the first input latch comprises a plurality of clock terminals each coupled to receive a respective phase of the fourth strobe signal from the second strobe generator circuit, the first input latch being operable to store a bit of read data coupled to the data bus terminal of the memory controller responsive to each transition of one of the phases of the fourth strobe signal coupled to the clock terminals of the first input latch, the first input latch having a plurality of output terminals coupling a respective bit of read data to the processor;

the second output latch comprises a plurality of input terminals each receiving from the array and storing a respective bit of read data, and a plurality of clock terminals each of which receives a respective one of the phases of the third strobe signal generated by the second strobe generator circuit, the second output latch being operable to couple a respective stored read data bit to the output terminal of the output latch responsive to each transition of one of the phases of the third strobe signal coupled to the clock terminals of the second output latch; and

the second input latch comprises a plurality of clock terminals each coupled to receive a respective phase of the second strobe signal from the first strobe generator circuit, the second input latch being operable to store a bit of write data coupled to the data bus terminal of the memory device responsive to each transition of one of the phases of the second strobe signal coupled to the clock terminals of the second input latch, the second input latch having a plurality of output terminals coupling a respective bit of write data to the memory array.

26. The computer system of claim 25 wherein the number of bits stored in the first and second output latches and the first and second input latches comprise four bits.

27. The computer system of claim 24 wherein the first and second strobe generator circuits each comprises:

a delay-lock loop receiving an input clock signal, the delay-lock loop comprising;

a phase detector having first input terminal receiving the input clock signal and second input terminal receiving a feedback clock signal, the phase detector being operable to generate at an output terminal a phase control voltage having a magnitude corresponding to the phase difference between input clock signal and the feedback clock signal; and

a delay line having an input coupled to receive the input clock signal, the delay line outputting a delayed clock signal having a phase relative to the phase of the input clock signal that is controlled by the phase control voltage;

a phase generator circuit coupled to receive the delayed clock signal from the delay line, the phase generator circuit generating the first or third strobe signals, respectively, and the second or fourth strobe signal, respectively, from the delayed clock signal; and

a feedback path coupling the first or third strobe signal to the second input of the phase detector as the feedback clock signal.

28. The computer system of claim 27 wherein the phase generator circuit comprises:

a second phase detector operable to generate a delay control signal corresponding to phase difference between first and second signals coupled to respective inputs of the second phase detector; and

a plurality of delay elements sequentially coupled to each other from a first delay element to a last delay element, each of the delay elements delaying a signal coupled to its input by a delay that is controlled by the delay control signal, the delayed clock signal being coupled to the first delay element, the first delay element generating the first signal coupled to the first input of the second phase detector, and the last delay element generating the second signal coupled to the second input of the second phase detector so that the phase of the first and second signals are equal to each other and respective phases of the strobe signals are generated at the outputs of respective ones of the delay elements.

29. The computer system of claim 28 wherein the plurality of delay elements comprise eight delay elements generating strobe signals having phases of 0, 45, 90, 135, 180, 225, 270, and 315 degrees, respectively.

30. The computer system of claim 24 wherein the memory comprises a dynamic random access memory array.

31. A method of coupling a command, address or data signal between a memory controller and a memory device, the method comprising:

generating a first strobe signal in one of the memory controller or memory device;

generating a second strobe signal in the memory controller or memory device where the first strobe signal is generated, the second strobe signal having signal transitions that are offset from signal transitions of the first strobe signal by 90 degrees;

coupling a command, address or data bit from the memory controller or memory device where the first strobe signal and second strobe signal are generated responsive to a transition of the first strobe signal;

coupling the second strobe signal to the other of the memory controller or memory device; and

capturing the command, address or data bit at the other of the memory controller or memory device responsive to a transition of the second strobe signal coupled to the other of the memory controller or memory device.

32. The method of claim 31 wherein the first strobe signal and the second strobe signal are generated in the memory controller, and wherein the command, address or data bit is coupled from the memory controller to the memory device and captured in the memory device.

33. The method of claim 32 wherein the command, address or data bit coupled from the memory controller to the memory device comprises a memory command bit.

34. The method of claim 32 wherein the command, address or data bit coupled from the memory controller to the memory device comprises a memory address bit.

35. The method of claim 32 wherein the command, address or data bit coupled from the memory controller to the memory device comprises a write data bit.

36. The method of claim 35, further comprising:

generating a third strobe signal in the memory device;

generating a fourth strobe signal in the memory device, the fourth strobe signal having signal transitions that are offset from signal transitions of the third strobe signal by 90 degrees;

coupling a read data bit from the memory device to the memory controller responsive to a transition of the third strobe signal;

coupling the fourth strobe signal to the memory controller; and

capturing the read data bit at the memory controller responsive to a transition of the fourth strobe signal coupled to the memory controller.

37. The method of claim 31 wherein the first strobe signal and the second strobe signal are generated in the memory device, and wherein the command, address or data bit coupled from the memory controller or memory device comprises a read data bit coupled from the memory device to the memory controller and captured in the memory controller.

38. The method of claim 31 wherein the act of generating a first strobe signal comprises generating a plurality of phases of the first strobe signal that differ from each other by N*180 degrees, and the act of generating a second strobe signal comprises generating a plurality of phases of the second strobe signal that differ from each other by N*180 degrees, where N is a positive integer.

39. The method of claim 38 wherein the act of coupling a command, address or data bit from the memory controller or memory device responsive to a transition of the first strobe signal comprises coupling a bit of the memory command, address or data from the memory controller or memory device responsive to each transition of one of the phases of the first strobe signal, and wherein the act of capturing the command, address or data bit at the other of the memory controller or memory device comprises storing a bit of the memory command, address or data coupled to the other of the memory controller or memory device responsive to each transition of one of the phases of the second strobe signal coupled to the other of the memory controller or memory device.

40. The method of claim 39 wherein the number of bits of the memory command, address or data coupled from the memory controller or memory device responsive to each transition of one of the phases of the first strobe signal and the number of bits of the memory command, address or data stored in the other of the memory controller or memory device responsive to each transition of one of the phases of the second strobe signal comprise four bits.

41. The method of claim 38 wherein the act of generating a plurality of phases of the first strobe signal comprises generating strobe signals having phases of 0 and 180 degrees, respectively, and the act of generating a plurality of phases of the second strobe signal comprises generating strobe signals having phases of 90 and 270 degrees, respectively.