Noise suppression in memory device sensing

• US 20060044908A1
• Filed: 09/02/2004
• Published: 03/02/2006
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ha, Chang Wan
• Granted Patent: US 7,079,434 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

Methods of sensing a programmed state of a nonvolatile memory cell, as well as apparatus for carrying out the methods, are useful in memory devices. Latches in sensing devices are selectively coupled to a variable-potential node to receive a first potential to switch the latch, i.e., presetting, setting or resetting the latch. After switching, the variable-potential node may be set to an intermediate potential to increase noise immunity to the latch while holding the data value. In NAND sensing devices having a data latch and a cache latch, the variable-potential nodes of the data latch and the variable-potential nodes of the cache latch are coupled to separate ground control circuits. By independently varying the potentials applied to the variable-potential nodes of the data latch and cache latch, determined by whether the individual latch is switching or holding data, noise immunity in the data path is increased.

Claims

1. A method of sensing a target memory cell, comprising:

applying a first potential to first variable-potential nodes associated with switching a first latch;

switching the first latch to a state indicative of a data value of the target memory cell while the first variable-potential nodes have their first potential;

applying a second potential to the first variable-potential nodes while holding the first latch in its state indicative of the data value;

applying a first potential to second variable-potential nodes associated with switching a second latch;

switching the second latch to a state indicative of the state of the first latch and of the data value while the second variable-potential nodes have their first potential and while the first variable-potential nodes have their second potential; and

applying a second potential to the second variable-potential nodes while holding the second latch in its state indicative of the data value.

2. The method of claim 1, wherein the first potential of the first variable-potential nodes is substantially equal to the first potential of the second variable-potential nodes.

3. The method of claim 1, wherein the first potential of the first variable-potential nodes is a ground potential.

4. The method of claim 3, wherein the second potential of the first variable-potential nodes is greater than the ground potential and less than or equal to a supply potential.

5. The method of claim 4, wherein the second potential of the first variable-potential nodes is approximately one Vt less than the supply potential.

6. The method of claim 1, wherein the first potential of the second variable-potential nodes is a ground potential.

7. The method of claim 6, wherein the second potential of the second variable-potential nodes is greater than the ground potential and less than or equal to a supply potential.

8. The method of claim 7, wherein the second potential of the second variable-potential nodes is approximately one Vt less than the supply potential.

9. The method of claim 1, further comprising:

applying the second potential to the second variable-potential nodes during at least a portion of a period of switching the first latch.

10. The method of claim 1, further comprising:

passing the state of the second latch to an output driver while applying the second potential to the second variable-potential nodes;

applying the first potential to the first variable-potential nodes during at least a portion of a period of passing the state of the second latch; and

switching the first latch to a state indicative of a data value of a second target memory cell while the first variable-potential nodes have their first potential.

11. A method of writing to a target memory cell, comprising:

applying a first potential to first variable-potential nodes associated with switching a first latch;

switching the first latch to a state indicative of a data value to be written to the target memory cell while the first variable-potential nodes have their first potential;

applying a second potential to the first variable-potential nodes while holding the first latch in its state indicative of the data value;

applying a first potential to second variable-potential nodes associated with switching a second latch;

switching the second latch to a state indicative of the state of the first latch and of the data value while the second variable-potential nodes have their first potential and while the first variable-potential nodes have their second potential;

applying a second potential to the second variable-potential nodes while holding the second latch in its state indicative of the data value; and

coupling the second latch to a bit line coupled to the target memory cell while applying the second potential to the second variable-potential nodes.

12. The method of claim 11, wherein the first potential of the first variable-potential nodes is substantially equal to the first potential of the second variable-potential nodes.

13. The method of claim 11, wherein the first potential of the first variable-potential nodes is a ground potential.

14. The method of claim 13, wherein the second potential of the first variable-potential nodes is greater than the ground potential and less than or equal to a supply potential.

15. The method of claim 14, wherein the second potential of the first variable-potential nodes is approximately one Vt less than the supply potential.

16. The method of claim 11, wherein the first potential of the second variable-potential nodes is a ground potential.

17. The method of claim 16, wherein the second potential of the second variable-potential nodes is greater than the ground potential and less than or equal to a supply potential.

18. The method of claim 17, wherein the second potential of the second variable-potential nodes is one Vt less than the supply potential.

19. The method of claim 11, further comprising:

applying the second potential to the second variable-potential nodes during at least a portion of a period of switching the first latch.

20. A method of passing data between latches in a sensing device of a memory device, the method comprising:

applying a first potential to first nodes associated with switching a first latch of the sensing device during a switching period of the first latch;

applying a second potential to the first nodes during a holding period of the first latch, wherein the second potential of the first nodes is greater than the first potential of the first nodes and less than a supply potential; and

passing a state of the first latch to a second latch of the sensing device during the holding period of the first latch.

21. The method of claim 20, wherein the first potential is a ground potential and the second potential is approximately one Vt less than the supply potential.

22. The method of claim 20, further comprising:

applying a first potential to second nodes associated with switching the second latch during a switching period of the second latch and while passing the state of the first latch to the second latch; and

applying a second potential to the second nodes during a holding period of the second latch, wherein the second potential of the second nodes is greater than the first potential of the second nodes and less than the supply potential.

23. The method of claim 22, wherein the first potential of the second nodes is substantially equal to the first potential of the first nodes and the second potential of the second nodes is substantially equal to the second potential of the first nodes.

24. The method of claim 22, wherein the holding period of the first latch is a different time period than the holding period of the second latch and wherein the switching period of the first latch is a different time period than the switching period of the second latch.

25. The method of claim 24, wherein the holding periods of the first and second latches overlap.

26. The method of claim 25, wherein the switching periods of the first and second latches do not overlap.

27. The method of claim 20, wherein the passing of the data occurs during one of a data read or a data write operation of the memory device.

28. A sensing device, comprising:

a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of a data value of a target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch; and

a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;

a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal; and

a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal.

29. The sensing device of claim 28, wherein each ground control circuit is coupled to receive a ground potential and a supply potential, and to provide its variable potential having either the ground potential or an intermediate potential between the ground potential and the supply potential.

30. The sensing device of claim 29, wherein the intermediate potential is approximately one Vt less than the supply potential.

31. The sensing device of claim 28, wherein the first ground control circuit and the second ground control circuit are adapted to provide the same potential levels, but independently of each other.

32. A memory device, comprising:

an array of memory cells; and

a sensing device for sensing a data value of a target memory cell of the array of memory cells, the sensing device comprising;

a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of the data value of the target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch; and

a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;

a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal; and

a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal;

wherein the first ground control circuit and the second ground control circuit are adapted to provide either a ground potential or an intermediate potential greater than the ground potential and less than a supply potential; and

wherein the first ground control circuit and the second ground control circuit are further adapted to provide their ground potentials or intermediate potentials independently of each other.

33. The memory device of claim 32, wherein the intermediate potential is approximately one Vt less than the supply potential.

34. An electronic device, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

an array of memory cells; and

a sensing device for sensing a data value of a target memory cell of the array of memory cells, the sensing device comprising;

a first latch for providing a first signal at a first node of the first latch and having a logic level indicative of the data value of the target memory cell, wherein the first latch is selectively coupled to one or more first variable-potential nodes for switching the first latch; and

a second latch for providing a second signal at a first node of the second latch and having a logic level indicative of the data value, wherein the second latch is selectively coupled to one or more second variable-potential nodes for switching the second latch;

a first ground control circuit coupled to receive a first control signal and to provide a variable potential to the first variable-potential nodes responsive to the first control signal; and

a second ground control circuit coupled to receive a second control signal and to provide a variable potential to the second variable-potential nodes responsive to the second control signal;

wherein the first ground control circuit and the second ground control circuit are adapted to provide either a ground potential or an intermediate potential approximately one Vt less than a supply potential; and

wherein the first ground control circuit and the second ground control circuit are further adapted to provide their ground potentials or intermediate potentials independently of each other.