Method for manufacturing display device

• US 20060046336A1
• Filed: 08/17/2005
• Published: 03/02/2006
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kawamata, Ikuko, Maekawa, Shinji, Suzuki, Yukie, Shoji, Hironobu, Honda, Tatsuya, Yamazaki, Shunpei, Yoshizumi, Kensuke
• Granted Patent: US 7,247,529 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 2102/3031 Two-side emission, e.g. transparent OLEDs [TOLED]
• CPC Class Codes: H10K 50/841 Self-supporting sealing arrangements
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 50/86 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 50/87 Arrangements for heating or cooling
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/38 comprising colour filters or colour changing media [CCM]
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/135 using ink-jet printing
• CPC Class Codes: Y02P 80/30 : Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

The present invention provides a method for manufacturing a display device having a TFT that can be operated at high speed while using a small number of photomasks and improving the utilization efficiency of materials, where the threshold value is difficult to be varied. In the invention, a catalytic element is applied to an amorphous semiconductor film and the amorphous semiconductor film is heated to form a crystalline semiconductor film. After removing the catalytic element from the crystalline semiconductor film, a top-gate type thin film transistor with a planar structure is manufactured. Moreover, by using the droplet discharging method where an element of a display device is formed selectively, the process can be simplified, and loss of materials can be reduced.

Claims

1. A method for manufacturing a display device, comprising:

forming an amorphous semiconductor layer over an insulated surface;

adding a metal element to the amorphous semiconductor layer and crystallizing the amorphous semiconductor layer by heating to form a crystalline semiconductor layer;

forming a semiconductor layer having one conductivity type in contact with the crystalline semiconductor layer;

heating the crystalline semiconductor layer and the semiconductor layer having one conductivity type;

patterning the semiconductor layer having one conductivity type to form a source region and a drain region;

discharging a composition containing a conductive material on the source region and the drain region to selectively form a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the crystalline semiconductor layer, the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating layer.

2. A method according to claim 1, wherein the gate electrode layer is formed by selectively discharging a composition that contains a conductive material.

3. A method according to claim 1,

wherein an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer, and

a pixel electrode layer is formed in the opening to be connected to the source electrode layer or the drain electrode layer.

4. A method according to claim 1, wherein an insulating layer is formed over the gate electrode layer and the gate insulating layer,

an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer and the insulating layer,

a wiring layer is formed in the opening to be in contact with the source electrode layer or the drain electrode layer, and

a pixel electrode layer is formed over the insulating layer in contact with the wiring layer.

5. A method according to claim 4, wherein the insulating layer is selectively formed by discharging a composition that contains an insulating material.

6. A method for manufacturing a display device, comprising:

forming an amorphous semiconductor layer over an insulated surface;

adding a metal element to the amorphous semiconductor layer and crystallizing the amorphous semiconductor layer by heating to form a crystalline semiconductor layer;

forming a channel protection layer over the crystalline semiconductor layer;

forming a semiconductor layer having one conductivity type over the crystalline semiconductor layer and the channel protection layer;

heating the crystalline semiconductor layer and the semiconductor layer having one conductivity type;

patterning the semiconductor layer having one conductivity type to form a source region and a drain region;

discharging a composition containing a conductive material on the source region and the drain region to selectively form a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the crystalline semiconductor layer, the channel protection layer, the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating layer.

7. A method according to claim 6, wherein the gate electrode layer is formed by selectively discharging a composition that contains a conductive material.

8. A method according to claim 6,

wherein an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer, and

a pixel electrode layer is formed in the opening to be connected to the source electrode layer or the drain electrode layer.

9. A method according to claim 6, wherein an insulating layer is formed over the gate electrode layer and the gate insulating layer,

an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer and the insulating layer,

a wiring layer is formed in the opening to be in contact with the source electrode layer or the drain electrode layer, and

a pixel electrode layer is formed over the insulating layer in contact with the wiring layer.

10. A method according to claim 9, wherein the insulating layer is selectively formed by discharging a composition that contains an insulating material.

11. A method for manufacturing a display device, comprising:

forming a first semiconductor layer over an insulated surface;

adding a metal element to the first semiconductor layer and heating the first semiconductor layer;

forming a second semiconductor layer including a first impurity element in contact with the first semiconductor layer;

heating the first semiconductor layer and the second semiconductor layer including the first impurity element;

removing the second semiconductor layer including the first impurity element;

adding a second impurity element to the first semiconductor layer to form a source region and a drain region;

discharging a composition containing a conductive material on the source region and the drain region to selectively form a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the crystalline semiconductor layer, the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating layer.

12. A method according to claim 11, wherein the second semiconductor layer including one or more of He, Ne, Ar, Kr, and Xe as the first impurity element is formed.

13. A method according to claim 11, wherein one or more kinds selected from phosphorus, nitrogen, arsenic, antimony and bismuth are added as the second impurity element.

14. A method according to claim 11, wherein the gate electrode layer is formed by selectively discharging a composition that contains a conductive material.

15. A method according to claim 11,

wherein an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer, and

a pixel electrode layer is formed in the opening to be connected to the source electrode layer or the drain electrode layer.

16. A method according to claim 11, wherein an insulating layer is formed over the gate electrode layer and the gate insulating layer,

an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer and the insulating layer,

a wiring layer is formed in the opening to be in contact with the source electrode layer or the drain electrode layer, and

a pixel electrode layer is formed over the insulating layer in contact with the wiring layer.

17. A method according to claim 16, wherein the insulating layer is selectively formed by discharging a composition that contains an insulating material.

18. A method for manufacturing a display device, comprising:

forming a first semiconductor layer over an insulated surface;

adding a metal element to the first semiconductor layer and heating the first semiconductor layer;

forming a second semiconductor layer including a first impurity element in contact with the first semiconductor layer;

heating the first semiconductor layer and the second semiconductor layer including the first impurity element;

removing the second semiconductor layer including the first impurity element;

forming a channel protection layer over a channel formation region of the first semiconductor layer;

adding a second impurity element to the first semiconductor layer to form a source region and a drain region;

discharging a composition containing a conductive material on the source region and the drain region to selectively form a source electrode layer and a drain electrode layer;

forming a gate insulating layer over the crystalline semiconductor layer, the channel protection layer, the source electrode layer and the drain electrode layer; and

forming a gate electrode layer over the gate insulating layer.

19. A method according to claim 18, wherein the second semiconductor layer including one or more of He, Ne, Ar, Kr, and Xe as the first impurity element is formed.

20. A method according to claim 18, wherein one or more kinds selected from phosphorus, nitrogen, arsenic, antimony and bismuth are added as the second impurity element.

21. A method according to claim 18, wherein the gate electrode layer is formed by selectively discharging a composition that contains a conductive material.

22. A method according to claim 18,

wherein an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer, and

a pixel electrode layer is formed in the opening to be connected to the source electrode layer or the drain electrode layer.

23. A method according to claim 18, wherein an insulating layer is formed over the gate electrode layer and the gate insulating layer,

an opening that reaches the source electrode layer or the drain electrode layer is formed in the gate insulating layer and the insulating layer,

a wiring layer is formed in the opening to be in contact with the source electrode layer or the drain electrode layer, and

a pixel electrode layer is formed over the insulating layer in contact with the wiring layer.

24. A method according to claim 23, wherein the insulating layer is selectively formed by discharging a composition that contains an insulating material.