ISFETs fabrication method

• US 20060046375A1
• Filed: 12/07/2004
• Published: 03/02/2006
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: National Yunlin University of Science and Technology
• Original Assignee: National Yunlin University of Science and Technology
• Inventors: Chou, Jung-Chuan, Liu, Shih I., Chen, Zhi Jie
• Granted Patent: US 7,067,343 B2
• Time in Patent Office: Days
• US Class Current: 438/216
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

Methods for fabricating ion sensitive field effect transistors (ISFETs) with SnO₂ extended gates. A SnO₂ detection film is formed on a substrate by sol-gel technology to serve as an extended gate. The SnO₂ detection film is electrically connected to a conductive wire, and an insulating layer is formed on the surface of the ISFET but part of the SnO₂ detection film and the conductive wire are left exposed. The exposed conductive wire is electrically connected to a gate terminal of a MOS transistor.

Claims

1. A fabrication method for ion sensitive field effect transistors (ISFETs) with a SnO₂ extended gate, comprising:

providing a substrate;

forming a SnO₂ detection film on the substrate by sol-gel technology to serve as an extended gate;

electrically connecting the SnO₂ detection film with a conductive wire;

forming an insulating layer on the surface of the ISFET but exposing part of the SnO₂ detection film and part of the conductive wire; and

electrically connecting the exposed conductive wire and a gate terminal of a MOS transistor.

2. The fabrication method as claimed in claim 1, wherein the insulating layer comprises epoxy resin.

3. The fabrication method as claimed in claim 1, wherein forming the SnO₂ detection film on the substrate comprises:

dissolving SnCl₂ powder by ethanol to form a mixed solution;

placing the mixed solution for a first predetermined duration to form a light yellow color mixed solution;

coating the light yellow color mixed solution on the substrate; and

heating the substrate to a first predetermined temperature for a second predetermined duration.

4. The fabrication method as claimed in claim 3, wherein the concentration of the solution comprising SnCl₂ and ethanol is about 0.37M.

5. The fabrication method as claimed in claim 4, wherein the first predetermined temperature is 350°

C.

6. The fabrication method as claimed in claim 4, wherein the second predetermined duration is 1 hour.

7. The fabrication method as claimed in claim 1, further comprising rinsing the substrate for a third predetermined duration by propyl alcohol, isopropanol and deionization water (DI water) respectively before forming the SnO₂ detection film.

8. The fabrication method as claimed in claim 7, wherein third predetermined duration is 20 minutes.

9. The fabrication method as claimed in claim 2, wherein connecting the SnO₂ detection film on substrate with the conductive wire comprises:

rinsing the substrate with the SnO₂ detection film by DI water;

fixing a first terminal of the conductive wire to the SnO₂ detection film by silver paste; and

heating the substrate to a second predetermined temperature for a fourth predetermined duration.

10. The fabrication method as claimed in claim 9, wherein the fourth predetermined duration is 10 minutes.

11. The fabrication method as claimed in claim 9, wherein forming an insulating layer on the surface of the ISFET comprises:

installing the conductive wire through a capillary;

packaging the substrate, the SnO₂ detection film, the conductive wire and capillary by the insulating layer but exposing part of the SnO₂ detection film, part of the conductive wire and part of the capillary; and

heating the substrate to the second predetermined temperature for a fifth predetermined duration.

12. The fabrication method as claimed in claim 11, wherein the second predetermined temperature is 120°

C.

13. The fabrication method as claimed in claim 11, wherein the fifth predetermined duration is 20 minutes.

19. A read circuit for ISFETs, comprising:

a detection circuit as claimed in claim 13, detecting the drain-source voltage and a drain-source current of the ISFET;

a processing unit coupled to the detection circuit, determining a pH value of an unknown solution according to the detected drain-source voltage and the detected drain-source current; and

a liquid crystal display coupled to the processing unit, displaying the determined pH value.

20. The detection circuit as in claim 19, wherein the processing unit is a PIC16F873 microprocessor.

14. A detection circuit for ISFETs, comprising:

a current mirror providing a reference current;

a first operational amplifier comprising a non-inversion input terminal coupled to the reference current and an inversion input terminal coupled to a drain terminal of an ISFET;

a first resistor comprising a first end coupled to the non-inversion input terminal of the first operational amplifier and a second end;

a second operational amplifier comprising a non-inversion input terminal coupled to a source terminal of the ISFET and an inversion input terminal coupled to the second end of the first resistor;

a drain-source voltage detection module coupled to the source terminal of the ISFET, detecting a drain-source voltage between the drain terminal and the source terminal of the ISFET; and

a drain-source current detection module coupled to the source terminal of the ISFET, detecting a drain-source current of the ISFET.

15. The detection circuit as claimed in claim 14, wherein the current mirror comprises:

a first transistor comprising a first terminal coupled to a first power voltage, a second terminal coupled to the first end of the first resistor, and a control terminal;

a second transistor comprising a first terminal coupled to the first voltage, a control terminal coupled to the control terminal of the first transistor, and a second terminal;

a third transistor comprising a first terminal coupled to the control terminals of the first and second transistors, a second terminal coupled to a ground voltage, and a control terminal coupled to the second terminal of the second transistor; and

a second resistor coupled between the ground voltage and the control terminal of the third transistor.

16. The detection circuit as claimed in claim 15, wherein the drain-source voltage detection module comprises:

a third operational amplifier comprising a non-inversion input terminal coupled to the drain terminal of the ISFET through a third resistor, an inversion input terminal coupled to the source terminal of the ISFET through a fourth resistor, and an output terminal;

a fifth resistor coupled between the output terminal and the inversion input terminal of the third operational amplifier;

a sixth resistor coupled between the ground voltage and the inversion input terminal of the third operational amplifier.

17. The detection circuit as claimed in claim 16, wherein the drain-source voltage detection module comprises:

a seventh resistor comprising a first end coupled to the ground voltage, and a second end;

a fourth transistor comprising a first terminal coupled to the ground voltage, a control terminal coupled to the second end of the seventh resistor, and a second terminal;

a fifth transistor comprising a first terminal coupled to second end of the seventh resistor, a second terminal coupled to a second power voltage, and a control terminal;

a sixth transistor comprising a first terminal coupled to the source terminal of the ISFET, a control terminal coupled to the control terminal of the fifth transistor, and a second terminal;

a seventh transistor comprising a first terminal coupled to the ground voltage through an eighth resistor, a control terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to the second terminal of the sixth transistor;

a ninth resistor comprising a first end coupled to the second terminals of the sixth and seventh transistors, and a second end coupled to the second power voltage; and

a fourth operational amplifier comprising a non-inversion input terminal coupled to the second terminal of the seventh transistor, and an inversion input terminal coupled to an output terminal thereof.

18. The detection circuit as claimed in claim 17, wherein the first and second resistors are variable resistors.