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DRAM cells with vertical transistors

  • US 20060046407A1
  • Filed: 09/01/2004
  • Published: 03/02/2006
  • Est. Priority Date: 09/01/2004
  • Status: Active Grant
First Claim
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1. A method for forming a transistor for an integrated circuit, the method comprising:

  • etching a semiconductor substrate to form a U-shaped silicon pillar pair and etched regions surrounding the U-shaped silicon pillar pair, wherein the silicon pillar pair comprises a first pillar and a second pillar;

    forming a first source/drain region in the first pillar;

    forming a second source/drain region in the second pillar; and

    forming a gate line in at least a portion of the etched regions, wherein the gate line at least partially surrounds the first and second pillars, wherein the first source/drain region, the second source/drain region, and at least a portion of the gate line form a U-shaped transistor.

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