DRAM cells with vertical transistors
First Claim
1. A method for forming a transistor for an integrated circuit, the method comprising:
- etching a semiconductor substrate to form a U-shaped silicon pillar pair and etched regions surrounding the U-shaped silicon pillar pair, wherein the silicon pillar pair comprises a first pillar and a second pillar;
forming a first source/drain region in the first pillar;
forming a second source/drain region in the second pillar; and
forming a gate line in at least a portion of the etched regions, wherein the gate line at least partially surrounds the first and second pillars, wherein the first source/drain region, the second source/drain region, and at least a portion of the gate line form a U-shaped transistor.
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Accused Products
Abstract
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
306 Citations
57 Claims
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1. A method for forming a transistor for an integrated circuit, the method comprising:
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etching a semiconductor substrate to form a U-shaped silicon pillar pair and etched regions surrounding the U-shaped silicon pillar pair, wherein the silicon pillar pair comprises a first pillar and a second pillar;
forming a first source/drain region in the first pillar;
forming a second source/drain region in the second pillar; and
forming a gate line in at least a portion of the etched regions, wherein the gate line at least partially surrounds the first and second pillars, wherein the first source/drain region, the second source/drain region, and at least a portion of the gate line form a U-shaped transistor. - View Dependent Claims (2, 3, 4)
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5. A method for forming a semiconductor device, the method comprising:
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etching a first set of trenches to a first depth into a semiconductor substrate;
etching a second set of trenches to a second depth into the semiconductor substrate, wherein the first set of trenches is substantially parallel to the second set of trenches, and wherein the first set of trenches and the second set of trenches are alternately spaced from one another within the semiconductor substrate;
etching a third set of trenches to a third depth into the semiconductor substrate, wherein the third set of trenches is substantially orthogonal to the first set of trenches and to the second set of trenches;
wherein the first, second, and third sets of trenches define an array of vertically extending pillars, wherein the array of vertically extending pillars comprises vertical source/drain regions; and
forming a gate line within at least a portion of the third set of trenches, wherein the gate line and the vertical source/drain regions form a plurality of transistors in which pairs of the source/drain regions are connected to one another through a transistor channel. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for forming a memory array, the method comprising:
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applying a device mask to a semiconductor substrate to form a first pattern of alternating first lines and first gaps on the semiconductor substrate;
processing the semiconductor substrate to form a first set of trenches, wherein the first set of trenches are formed within the semiconductor substrate within at least a portion of the area defined by the first gaps;
applying a periphery mask to the semiconductor device after forming the first set of trenches, wherein the periphery mask protects a periphery adjacent an array region;
processing the semiconductor substrate to form a second set of trenches substantially parallel to the first set of trenches, wherein the second set of trenches are formed within the semiconductor substrate within at least a portion of the array region;
applying a wordline mask to the semiconductor device to form a second pattern of alternating second lines and second gaps on the semiconductor substrate after forming the second set of trenches, wherein the second lines and second gaps intersect with paths of the first lines and first gaps; and
processing the semiconductor substrate to form a third set of trenches, wherein the third set of trenches are formed within the semiconductor substrate within at least a portion of the area defined by the second gaps, and not formed in the protected periphery. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for forming a plurality of U-shaped transistors in a semiconductor structure, the method comprising:
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separating first and second pillars of each U-shaped transistor by a plurality of first trenches; and
separating each U-shaped transistor from an adjacent U-shaped transistor by a plurality of second trenches that extend deeper into a semiconductor substrate than the first trenches. - View Dependent Claims (25, 26, 27, 28)
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29. An integrated circuit comprising:
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a semiconductor substrate;
first and second U-shaped transistors formed within the semiconductor substrate, the first and second U-shaped transistors separated by a first trench that extends deeper into the semiconductor substrate than the first and second U shaped transistors; and
a second trench that separates the first and second U-shaped transistors from third and fourth U-shaped transistors, wherein the second trench extends into the semiconductor substrate and is shallower than the first trench. - View Dependent Claims (30, 31, 32, 33)
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34. A memory cell comprising:
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a semiconductor substrate; and
a U-shaped transistor formed within the semiconductor substrate, the U-shaped transistor comprising a first pillar and a second pillar, wherein the first and second pillars are separated by a trench that extends into the semiconductor substrate;
a memory storage device, the memory storage device connected to the first pillar; and
a digit line, the digit line connected to the second pillar. - View Dependent Claims (35, 36, 37, 38, 39, 40)
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41. A semiconductor structure comprising:
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a plurality of columns of protrusions, wherein each protrusion includes a source, a drain, and a channel;
a plurality of wordline gaps separating the columns from one another; and
a plurality of gate lines formed within the wordline gaps, each gate line at least partially surrounding one of the columns. - View Dependent Claims (42, 43, 44)
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45. An electronic device comprising:
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at least one U-shaped semiconductor structure having a first U-shaped surface and a second U-shaped surface on opposite sides connected by end-walls, wherein the first and second U-shaped surfaces are substantially parallel, the U-shaped semiconductor structure comprising a first source/drain region and a second source/drain region;
a first channel formed along the first U-shaped surface;
a second channel formed along the second U-shaped surface;
a gate line facing both U-shaped surfaces; and
a field isolation element directly adjacent each end-wall. - View Dependent Claims (46)
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47. A method of forming a memory cell comprising:
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etching a semiconductor substrate to form at least one U-shaped transistor having a first U-shaped surface and a second U-shaped surface, wherein the first and second U-shaped surfaces are substantially parallel, the U-shaped transistor comprising a first source/drain region, a second source/drain region, and a gate line, wherein the first source/drain region and the second source drain region are formed within the semiconductor substrate;
forming a first channel within the semiconductor substrate along the first U-shaped surface;
forming a second channel within the semiconductor substrate along the second U-shaped surface; and
forming the gate line facing each of the first and second channels. - View Dependent Claims (48, 49)
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50. A method of forming a semiconductor structure comprising:
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etching a set of wordline trenches within a semiconductor substrate;
etching a set of deep trenches within a semiconductor substrate, the set of deep trenches crossing and creating a grid with the set of wordline trenches, wherein the set of wordline trenches and the set of deep trenches define a plurality of protrusions within the semiconductor substrate;
defining a heavily doped region and a lightly doped region within each protrusion;
depositing gate material into the set of wordline trenches; and
spacer etching the gate material to define a gate electrode on sidewalls of the protrusion. - View Dependent Claims (51, 52, 53, 54)
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55. A semiconductor structure comprising:
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a semiconductor substrate;
a U-shaped protrusion surrounded by a set of wordline trenches and a set of deep trenches etched into the semiconductor substrate, the U-shaped protrusion comprises a first pillar and a second pillar, wherein the first and second pillars are separated by a shallow trench of a set of shallow trenches that extends into the semiconductor substrate and wherein the first and second pillars are connected by a ridge that extends above the surrounding trenches;
a first source/drain region formed at a top portion of the first pillar;
a second source/drain region formed at a top portion of the second pillar; and
a gate structure formed in the set of wordline trenches;
wherein the ridge and the lower portions of the first and second pillars define U-shaped channels on opposite sides of the U-shaped protrusion, wherein the U-shaped channels face the gate structure formed in the set of wordline trenches. - View Dependent Claims (56, 57)
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Specification