Edge-aligned ratio counter
First Claim
1. A circuit comprising at least one processor coupled to at least one counter circuit, the counter circuit receiving one of a first and second value in response to a first clock signal and generating a control signal under control of the received value, the counter circuit counting pulses of a first clock signal and a second clock signal and capturing the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the captured count.
2 Assignments
0 Petitions
Accused Products
Abstract
An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control of the loaded value by counting the pulses of the first clock signal and a second clock signal and captures the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the differences of the captured counts taken at two different occurrences of the control signal.
39 Citations
30 Claims
- 1. A circuit comprising at least one processor coupled to at least one counter circuit, the counter circuit receiving one of a first and second value in response to a first clock signal and generating a control signal under control of the received value, the counter circuit counting pulses of a first clock signal and a second clock signal and capturing the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the captured count.
-
17. A communications device comprising:
-
at least one processor;
at least one memory area coupled to the processor and storing values representative of a first clock signal and a second clock signal; and
at least one counter circuit coupled to the processor and selectively receiving the stored values and generating a control signal under control of the stored values, the counter circuit counting pulses of the first and second clock signals, capturing the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first and second clock signals using the captured count. - View Dependent Claims (18, 19, 20, 21)
-
-
22. A device comprising:
-
means for receiving one of a first and second value in response to a first clock signal;
means for generating a control signal under control of the received value;
means for counting pulses of a first clock signal and a second clock signal and capturing the count of each clock signal in response to the control signal; and
means for determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the captured count. - View Dependent Claims (23, 24, 25)
-
-
26. A method comprising:
-
receiving one of a first and second value in response to a first clock signal;
generating a control signal under control of the received value;
counting pulses of a first clock signal and a second clock signal and capturing the count of each clock signal in response to the control signal; and
determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using differences of successive captured count, respectively. - View Dependent Claims (27, 28, 29, 30)
-
Specification