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System and method for transmitting data packets in a computer system having a memory hub architecture

  • US 20060047891A1
  • Filed: 08/31/2004
  • Published: 03/02/2006
  • Est. Priority Date: 08/31/2004
  • Status: Active Grant
First Claim
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1. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:

  • an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs;

    a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;

    a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;

    a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and

    a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage.

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