System and method for transmitting data packets in a computer system having a memory hub architecture
First Claim
1. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:
- an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;
a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage.
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Accused Products
Abstract
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.
142 Citations
42 Claims
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1. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:
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an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;
a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 22)
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12. A memory system, comprising:
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a memory controller;
a plurality of memory hubs, each memory hub being coupled to adjacent memory hubs through respective links, at least one of the memory hubs being coupled to the memory controller through an upstream link;
a system for transmitting data packets from the memory hub to the memory controller, over the upstream link comprising;
an upstream reception port coupled to a downstream memory hub and operable to receive data packets from the downstream memory hub;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;
a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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23. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:
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an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;
an upstream buffer coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass FIFO coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the upstream buffer, the bypass FIFO or the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, the upstream buffer or the bypass FIFO. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 40, 41, 42)
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32. A method for transmitting data packets from a memory hub to a memory controller over an upstream link, the data packets originating from a local memory and downstream hubs of the computer system, comprising:
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transmitting the data packets from the downstream hubs by coupling a bypass bus to the upstream link;
transmitting the data packets from the local memory by coupling the local memory to the upstream link;
storing the data packets from the downstream hubs in a temporary storage while the data packets from the local memory are being transmitted; and
transmitting the data packets from the temporary storage by coupling the temporary storage to the upstream link. - View Dependent Claims (33, 34, 35)
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Specification