Method and apparatus for transmitting memory pre-fetch commands on a bus

• US 20060047914A1
• Filed: 08/27/2004
• Published: 03/02/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Schaffer, Mark Michael, Hofmann, Richard Gerard
• Granted Patent: US 8,028,143 B2
• Time in Patent Office: Days
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

Claims

1. A method of retrieving data from memory, comprising:

predicting an address of the memory from which data will be needed;

transmitting to a memory controller a pre-fetch command for the data at the predicted address of the memory;

transmitting to the memory controller a read request for the data at the predicted address of the memory; and

receiving the data at the predicted address of the memory in response to the read request.

2. The method of claim 1 wherein the memory controller opens a page in the memory in response to the pre-fetch command, the page including the data at the predicted address.

3. The method of claim 2 wherein the memory controller reads into a pre-fetch buffer at least a portion of the data from the page including the data at the predicted address, and wherein the data at the predicted address is received from the pre-fetch buffer in response to the read request.

4. The method of claim 3 wherein the size of said at least a portion of the data from the page read into the pre-fetch buffer is a predetermined size.

5. The method of claim 3 wherein the size of said at least a portion of the data from the page read into the pre-fetch buffer is transmitted to the memory controller with the pre-fetch command.

6. The method of claim 1 wherein the memory comprises SDRAM.

7. The method of claim 1 wherein the memory comprises NAND Flash memory.

8. The method of claim 1 further comprising transmitting the predicted address to the memory controller with the pre-fetch command and the read request.

9. The method of claim 8 wherein the predicted address is transmitted to the memory controller on a first channel of a bus, and wherein the data is received in response to the read request on a second channel of the bus.

10. The method of claim 9 wherein the pre-fetch command and the read request are transmitted to the memory controller on a common channel.

11. The method of claim 10 wherein the pre-fetch command comprises a first code and the read request comprises a second code different from the first code.

12. The method of claim 9 further comprising transmitting transfer qualifiers associated with the pre-fetch command and the read request to the memory controller on the first channel of the bus.

13. The method of claim 9 further comprising transmitting data to be written to the memory on the first channel of the bus, and transmitting an address to write the data to the memory on the first channel of the bus.

14. A method of retrieving data from memory, comprising:

predicting an address from an unopened page of the memory from which data will be needed;

transmitting to a memory controller a pre-fetch command for the data at the predicted address of the memory;

reading the data at the predicted address into a pre-fetch buffer; and

discarding the data from the pre-fetch buffer.

15. The method of claim 14 wherein the data is discarded from the pre-fetch buffer in response to the transmission to the memory controller of a predetermined number of the read requests for data from one or more different pages of the memory without a read request for the data at the predicted address in the memory being transmitted to the memory controller.

16. The method of claim 14 wherein the data is discarded from the pre-fetch buffer after a predetermined time without a read request for the data at the predicted address in the memory being transmitted to the memory controller.

17. The method of claim 14 wherein the data is discarded by the pre-fetch buffer in response to a subsequent pre-fetch command transmitted to the memory controller before a read request for the data at the predicted address in the memory is transmitted to the memory controller.

18. A processing system, comprising:

memory;

a memory controller; and

a processor configured to predict an address of the memory from which data will be needed, transmit to the memory controller a pre-fetch command for the data at the predicted address of the memory; and

transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed;

wherein the memory controller is further configured to deliver the data at the predicted address of the memory to the processor in response to the read request.

19. The processing system of claim 18 wherein the memory controller is further configured to open a page in the memory in response to the pre-fetch command, the page including the data at the predicted address.

20. The processing system of claim 19 further comprising a pre-fetch buffer;

and wherein the memory controller is further configured to read into the pre-fetch buffer at least a portion of the data from the page including the data at the predicted address, and to deliver the data at the predicted address to the processor from the pre-fetch buffer in response to the read request.

21. The processing system of claim 20 wherein the size of said at least a portion of the data from the page read into the pre-fetch buffer is a predetermined size.

22. The processing system of claim 20 wherein the processor is further configured to transmit to the pre-fetch buffer the size of said at least a portion of the data from the page to be read into the pre-fetch buffer.

23. The processing system of claim 20 wherein the pre-fetch buffer is located in the memory controller.

24. The processing system of claim 20 wherein the memory controller is further configured to discard the data in the pre-fetch buffer if the memory controller receives from the processor a predetermined number of read requests for data from one or more different pages of the memory after the pre-fetch command without receiving the read request for the data at the predicted address of the memory.

25. The processing system of claim 18 wherein the memory comprises SDRAM.

26. The processing system of claim 18 wherein the memory comprises NAND Flash memory.

27. The processing system of claim 18 wherein the processor is further configured to transmit the predicted address to the memory controller with the pre-fetch command and the read request.

28. The processing system of claim 27 further comprising a bus coupling the processor to the memory controller, the bus having first and second channels, wherein the processor is further configured to transmit the predicted address to the memory controller on a first channel of a bus, and wherein the memory controller is further configured to transmit the data to the processor on the second channel of the bus.

29. The processing system of claim 28 further comprising a common channel between the processor and the memory controller, and wherein processor is further configured to transmit the pre-fetch command and the read request to the memory controller on the common channel.

30. The processing system of claim 29 wherein the processor is further configured to generate a first code comprising the pre-fetch command and a second code comprising the read request, the first code being different from the second code.

31. The processing system of claim 28 wherein the processor is further configured to transmit transfer qualifiers associated with the pre-fetch command and the read request to the memory controller on the first channel of the bus.

32. The processing system of claim 28 wherein the processor is further configured to transmit data to be written to the memory on the first channel of the bus, and transmit an address to write the data to the memory on the first channel of the bus.

33. A processing system, comprising:

memory;

a memory controller;

means for predicting an address of the memory from which data will be needed;

means for transmitting to the memory controller a pre-fetch command for the data at the predicted address of the memory;

means for transmitting to the memory controller a read request for the data at the predicted address of the memory if the data is needed; and

receiving means for receiving the data;

wherein the memory controller is further configured to deliver the data at the predicted address of the memory to the receiving means in response to the read request.