SIMD processor and addressing method

• US 20060047937A1
• Filed: 08/30/2004
• Published: 03/02/2006
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Selvaggi, Richard J., Pearlstein, Larry A.
• Granted Patent: US 7,434,024 B2
• Time in Patent Office: Days
• US Class Current: 711/220
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3555 using scaling, e.g. multiplication of index

Abstract

A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set'"'"'s pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value.

Claims

1. A method of executing an instruction using a processor, said processor having a plurality of addressing register sets, each register set comprising a pointer register and a scale register, said method comprising calculating an effective memory address for use by said processor in executing said instruction, said calculating comprising:

determining a selected one of said register sets from said processor instruction;

retrieving a pointer stored in said pointer register of said selected one of said register sets;

retrieving a scale value stored in said scale register of said selected one of said register sets;

forming an effective memory address from said scale value and said pointer.

2. The method of claim 1, wherein said forming comprises multiplying said scale value by an offset value and summing said pointer and said scale value multiplied by said offset value, to form said effective memory address.

3. The method of claim 2, wherein said offset value comprises a part of a processor readable representation of said instruction.

4. The method of claim 2, wherein said offset value is stored in a third register of said processor.

5. The method of claim 2, wherein each of said register sets further comprises an increment register, and said method further comprises updating said pointer in said pointer register of said selected one of said register sets by a value stored in said increment register of said selected one of said register sets, after performing an arithmetic or logical operation specified by said instruction.

6. The method of claim 2, wherein said offset value comprises the sum of a displacement value and a loop value stored in a loop register maintained by said processor in response to executing a defined loop of instructions.

7. The method of claim 6, wherein said offset value is formed from said loop value in response to an indicator in a part of a processor readable representation of said instruction.

8. The method of claim 2, wherein said pointer register and said scale register of said selected one of said register sets in a single clock cycle of said processor.

9. The method of claim 2, further comprising retrieving data stored at said effective memory address for use as a source operand, and applying an arithmetic or logical operation specified by said instruction identically to portions of said source operand.

10. In a processor having at least two register sets, each of said register sets comprising a pointer register containing a memory address and an associated increment register, a method of executing an instruction comprising:

retrieving data stored at a memory address based on a pointer register of a first one of said sets, for use as a first operand;

performing an arithmetic or logical operation in accordance with said instruction on said first operand to produce a result;

updating said pointer register of said first set by incrementing said pointer register of said first set based on a value contained in its associated increment register.

11. The method of claim 10, further comprising retrieving data stored at a memory address based on a pointer register of a second one of said sets, for use as a second operand;

and performing said arithmetic or logical operation in accordance with said instruction on said first and second operand to produce said result.

12. The method of claim 11, further comprising updating said pointer register of said second set by incrementing said pointer register of said second set based on a value contained in its associated increment register.

13. The method of claim 11, wherein each of said first and second sets each further comprises a displacement register and said memory address is further based on a displacement register of one of said sets.

14. The method of claim 10, further comprising storing said result at an address defined at least in part by a pointer register of a third one of said sets.

15. The method of claim 10, further comprising applying said arithmetic or logical operation in accordance with said instruction identically to portions of said first operand.

16. A processor for connection with processor-readable memory, said processor comprising:

first and second address generators for generating first and second operand memory addresses, respectively;

first and second sets of registers, in communication with said first and second address generators, each of said first and second set of registers comprising a pointer register and a scale factor register;

said first operand memory address generated by summing values in said scale register of said first set of registers multiplied by a first offset value and said pointer register of said first set of registers;

said second operand memory addresses generated as summing values in said scale register of said second set of registers multiplied by a second offset value and said pointer register of said second set of registers;

an arithmetic logic unit in communication with memory for performing an arithmetic or logical operation specified by an instruction, on operands stored at said first and second operand memory addresses of said processor readable memory.

17. The processor of claim 16, wherein said first address generator generates a first even memory address and a first odd memory address, and wherein said processor readable memory is addressable in memory data units having a defined bit size, said processor further comprising

a memory interface to obtain data at said first odd memory address having said defined bit size, and data at said first even memory address having said defined bit size;

a combiner for combining said data stored in said first and second memory data units to form said data at said first operand memory address.

18. The processor of claim 17, further comprising:

a third address generator;

a third set of registers, in communication with said third address generators and comprising a pointer register and a scale factor register;

said third address generators, for generating a write memory address for storing the results of said arithmetic or logical operation, by summing values in said scale factor register of said third set of registers multiplied by a third offset value and said pointer register of said third set of registers.

19. The processor of claim 18, wherein said arithmetic logic unit applies said operation specified by said instruction identically to portions of said operands stored at said first and second operand memory addresses of said processor readable memory.

20. The processor of claim 19, wherein said first set of registers further comprises an increment register used to post-increment said pointer register of said first set of registers by a value of said increment register of said first set of registers after said arithmetic logic unit has performed said arithmetic or logical operation.

21. The processor of claim 20, wherein said second set of registers further comprises an increment register, used to post increment said pointer register of said second set by a value of said increment register after said arithmetic logic unit has performed said arithmetic instruction.

22. The processor of claim 21, wherein said first set of registers comprises a mode register, and said mode register dictates if said pointer register of said first set of registers is post incremented.

23. The processor of claim 22, wherein said second set of registers comprises a mode register, and said mode register dictates if said pointer register of said second set of registers is post incremented.

24. The processor of claim 16, further comprising a loop index register, and said first operand address is generated by further summing thereto values in said loop index register multiplied by said scale factor register of said first set of registers.

25. The processor of claim 21, wherein said instruction includes at least one mode indicator indicating whether one of said pointer registers of one of said first and second sets of registers is post incremented.

26. A single instruction, multiple data (SIMD) processor comprising a memory interface for accessing memory addressable in data units of a defined bit size, said memory interface comprising:

an address generator for generating first and second addresses of memory to be read;

a memory interconnect to obtain data units at said first address having said defined bit size, and at said second address having said defined bit size;

a combiner for combining said data units from said first and second memory addresses to form an operand spanning said first and second memory addresses.

27. The processor of claim 26, wherein said first and second addresses are adjacent even and odd addresses.

28. The processor of claim 27, wherein said address generator generates said addresses concurrently.

29. In a processing system comprising a processor and memory, wherein said memory is addressable by said processor in memory data units having a defined bit size, a method of retrieving a source data unit spanning first and second ones of said memory data units, said method comprising:

simultaneously addressing said memory to access said first and second ones of said memory data units;

retrieving data stored in said first and second ones of said memory data units;

combining said data stored in said first and second memory data units to form said source data unit.

30. The method of claim 29, wherein said source data unit has a bit size smaller than said defined bit size.

31. The method of claim 30, wherein said simultaneously addressing comprises addressing even and odd banks of said memory, to access said first and second ones of said memory data units, respectively.

32. The method of claim 30, wherein said simultaneously addressing comprises addressing dual ported memory.

33. The method of claim 32, wherein said combining comprises shifting said retrieved data by a selected number of bits in dependence on said defined bit size.

34. The method of claim 32, further comprising reversing an order of said first and second ones of said memory data units, prior to said retrieve.

35. In a processing system comprising a single instruction, multiple data (SIMD) processor and memory, wherein said memory is addressable by said processor in memory data units having a defined bit size, a method of storing a resulting data unit spanning first and second ones of said memory data units, said method comprising:

splitting said resulting data unit into first and second data portions;

said first data portion to be stored in said first of said memory data units;

said second data portion to be stored in said second memory data units;

generating a first masking instruction to cause a memory element storing said first data unit to mask writing to said data unit at bits not occupied by said first data portion;

generating a second masking instruction to cause a memory element storing said second data unit to mask writing to said data unit at bits not occupied by said second data portion;

providing said first and second masking instructions to memory storing said first and second data units;

storing said first data portion into the portion of said first memory data unit according to said first masking instruction and concurrently storing said second data portion at a portion of said second memory data unit according to said second masking instruction.

36. The method of claim 35, wherein said first and second data portions have an equal bit size.

37. A method of operating a processor executing sequential instructions, comprising:

receiving a stream of data;

buffering a portion of said stream, in a first-in, first-out buffer within memory of said processor;

reading data from said first-in-first out buffer, by said processor;

encountering an instruction to read data in said stream not yet received in said buffer;

stalling execution of said instruction and further ones of said sequential instructions until said data within said stream specified by said instruction has been received in said first-in, first-out buffer.

38. The method of claim 37, wherein said stream is received from a direct memory access (DMA) engine.

39. The method of claim 38, wherein said reading further comprises calculating a read address, and said stalling further comprises comparing said read address to addresses occupied by said first-in, first-out buffer.

40. A processor that executes instructions stored in instruction memory, said processor comprising:

memory defining a first-in, first-out buffer for buffering a portion of a data stream;

an arithmetic or logic unit (ALU), for processing data within said memory;

an address generator for generating a memory address of said memory to be read by said ALU;

an interlock, operable to generate a stall signal to stall execution of a currently executing instruction in said instruction memory in response to generating an address to access data in said buffer, not yet containing data in said stream.

41. The processor of claim 40, further comprising interconnects for interconnecting said processor to a DMA engine that may access said buffer to write said stream.

42. A processor that executes instruction stored in instruction memory, said processor comprising:

memory defining a first-in, first-out buffer for buffering a portion of a data stream, to be read in a stream by a device other than said processor;

an arithmetic or logic unit (ALU), for processing data within said memory;

an address generator for generating a memory address of said memory to be written to by said ALU;

an interlock, operable to generate a halt signal to halt execution of a currently executing instruction in said instruction memory in response to said address generator generating an address to write to an address in said first-in, first-out buffer containing data, not yet read by said other device.

43. A method of operating a processor executing sequential instructions, comprising:

buffering a portion of a stream of data to be written, in a first-in, first-out buffer within memory of said processor;

providing data from said first-in, first-out buffer to a device other than said processor;

writing data to said first-in-first out buffer, by said processor;

encountering an instruction to write data to said first-in, first out buffer at addresses containing data not yet provided from said first-in, first-out buffer;

stalling execution of said instruction and further ones of said sequential instructions until said data within said first-in, first-out buffer specified by said instruction has been provided from said first-in, first-out buffer.

44. The method of claim 43, wherein said stream is provided to a direct memory access (DMA) engine.

45. The method of claim 44, wherein said writing further comprises calculating a write address, and said stalling further comprises comparing said write address to addresses occupied by said first-in, first-out buffer.

46. Computer readable memory storing instructions for execution by a processor comprising a plurality of register sets, said memory storing a single instruction, multiple data processor executable instruction comprising:

a plurality of bits identifying an op code;

a plurality of bits identifying a first one of said register sets used to form

a memory address of a first operand;

a plurality of bits identifying a second one of said register sets used to form a memory address of a second operand;

a plurality of bits identifying a third one of said register sets used to calculate a destination address, for storing a result of said op code operating on said first and second operands.