Data storage apparatus and control method thereof

• US 20060047985A1
• Filed: 08/22/2005
• Published: 03/02/2006
• Est. Priority Date: 08/31/2004
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Otani, Atsushi
• Granted Patent: US 7,594,129 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides a data storage apparatus capable of reducing an amount of electric current flowing in a bus. The data storage apparatus includes a data storage unit adapted to store data, a plurality of buffer units adapted to output data to the data storage unit through a bus, wherein the bus includes a plurality of signal lines, and wherein the plurality of buffer units are provided on the plurality of signal lines, a determination unit adapted to determine whether the bus is in an operating state in which transmission and reception of data to and from the data storage unit are performed, a reference voltage supply unit adapted to supply a predetermined reference voltage to the plurality of signal lines, a control unit adapted to control, in a case where the determination unit determines that a state of the bus is changed from an operating state to a nonoperating state, the plurality of buffer units to switch output states to predetermined output states to reduce an amount of electric current flowing in the bus through the reference voltage supply unit.

Claims

1. A data storage apparatus comprising:

a data storage unit adapted to store data;

a plurality of buffer units, adapted to output data to the data storage unit through a bus, wherein the bus includes a plurality of signal lines, and wherein the plurality of buffer units are provided on the plurality of signal lines;

a determination unit adapted to determine whether the bus is in an operating state in which transmission and reception of data to and from the data storage unit are performed;

a reference voltage supply unit adapted to supply a predetermined reference voltage to the plurality of signal lines; and

a control unit adapted to control, in a case where the determination unit determines that a state of the bus is changed from the operating state to a nonoperating state, the plurality of buffer units to switch output states to predetermined output states to reduce an amount of electric current flowing in the bus through the reference voltage supply unit.

2. The data storage apparatus according to claim 1, further comprising:

a power-supply-voltage supplying unit adapted to supply a predetermined power supply voltage to the data storage apparatus,

wherein the predetermined reference voltage supplied by the reference voltage supply unit is approximately half the power supply voltage supplied by the power-supply-voltage supplying unit.

3. The data storage apparatus according to claim 1, further comprising:

an output state storage unit adapted to store information on the predetermined output states,

wherein the control unit controls the plurality of buffer units to switch the output states to the predetermined output states according to the information on the predetermined output states, which is stored in the output state storage unit.

4. The data storage apparatus according to claim 1, further comprising:

a second determination unit adapted to determine whether the bus is in an active state in which the bus is enabled to perform transmission and reception of data to and from the data storage unit, and

wherein the control unit brings, in a case where the second determination unit determines that the bus is not in the active state, the output states of the plurality of buffer units into a high impedance state.

5. The data storage apparatus according to claim 1,

wherein the data storage unit is a DRAM adapted to perform a predetermined refresh operation so as to hold data, and

wherein the data storage apparatus further comprises a transmission unit adapted to transmit, to the DRAM through the bus, a signal which causes the DRAM to perform the refresh operation.

6. The data storage apparatus according to claim 5,

wherein the DRAM performs a refresh operation in one of a first refresh mode in which the refresh operation is performed according to the signal inputted through the bus which causes the DRAM to perform the refresh operation, and a second refresh mode in which the refresh operation is performed without using the signal which causes the DRAM to perform the refresh operation.

7. The data storage apparatus according to claim 6,

wherein the transmission units transmits a signal, which switches the first refresh mode to the second refresh mode, in response to change of a state of the bus from an active state to an inactive state.

8. The data storage apparatus according to claim 1,

wherein in response to change of a state of the bus from an active state to an inactive state, a state of the reference voltage supply unit changes from a supplying state in which the reference voltage supply unit supplies the reference voltage to the bus to a non-supplying state, in which the reference voltage supply unit does not supply the reference voltage to the bus.

9. The data storage apparatus according to claim 6,

wherein the DRAM performs the refresh operation without responding to a signal inputted through the transmission unit in a case where the DRAM performs the refresh operation in the second refresh mode.

10. A method of controlling a data storage apparatus, comprising the steps of:

determining whether a bus having a plurality of signal lines is in an operating state in which the bus performs transmission and reception of data to and from a data storage unit; and

controlling, in a case where a state of the bus is determined in the determining step to be changed from the operating state to a nonoperating state, a plurality of buffer units respectively provided on the plurality of signal lines to switch output states to predetermined output states so as to reduce an amount of electric current flowing in the bus through a reference voltage supply unit adapted to supply a predetermined reference voltage to the bus.

11. The method of controlling a data storage apparatus, according to claim 10,

wherein a predetermined power supply voltage is supplied to the data storage apparatus, and

wherein the predetermined reference voltage is approximately half the power supply voltage.

12. The method of controlling a data storage apparatus, according to claim 10, further comprising a step of:

storing information on the predetermined output states,

wherein the controlling step is performed according to the information on the predetermined output states stored in the storing step.

13. The method of controlling a data storage apparatus, according to claim 10, further comprising:

a second determining step determining whether the bus is in an active state in which the bus is enabled to perform transmission and reception of data to and from the data storage unit,

wherein the controlling step includes a step of;

bringing, in a case where the bus is determined in the second determining step not to be in the active state, the output states of the plurality of buffer units into a high impedance state.

14. The method of controlling a data storage apparatus, according to claim 10,

wherein the data storage unit is a DRAM adapted to perform a predetermined refresh operation so as to hold data, and

wherein the method further comprises a step of transmitting a signal through the bus which causes the DRAM to perform the predetermined refresh operation.

15. The method of controlling a data storage apparatus, according to claim 14, further comprising a step of:

refreshing the DRAM in one of a first refresh mode in which the refresh operation is performed according to the signal transmitted in the transmitting step and inputted through the bus which causes the DRAM to perform the refresh operation, and a second refresh mode in which the refresh operation is performed without using the signal which causes the DRAM to perform the refresh operation.

16. The method of controlling a data storage apparatus, according to claim 15,

wherein the transmitting step includes a step of transmitting a signal which switches the first refresh mode to the second refresh mode, in response to change of a state of the bus from an active state to an inactive state.

17. The method of controlling a data storage apparatus, according to claim 13, further comprising a step of:

controlling the reference voltage supply unit to change a state from a supplying state in which the reference voltage supply unit supplies the reference voltage to the bus to a non-supplying state in which the reference voltage supply unit does not supply the reference voltage to the bus, in response to a determination made in the second determining step which indicates that a state of the bus is changed from an active state to an inactive state.

18. The method of controlling a data storage apparatus, according to claim 15,

wherein the refreshing step includes a step of performing, in a case where the DRAM is refreshed in the second refresh mode, the refresh operation without responding to the signal inputted in the transmitting step.

19. Computer-executable process steps for executing the method of claim 10.

20. A computer-readable storage medium for storing the computer-executable process steps of claim 19.