Systems and methods for synchronizing the internal clocks of a plurality of processor modules

• US 20060047989A1
• Filed: 08/24/2004
• Published: 03/02/2006
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Veritas Technologies, LLC (Whitehouse Group Ltd.)
• Original Assignee: Symantec Operating Corporation (Gen Digital Inc.)
• Inventors: Darcy, Jeff, Delgado, Diane
• Granted Patent: US 7,239,581 B2
• Time in Patent Office: Days
• US Class Current: 713/375
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

In a multiprocessor system that includes a plurality of processor modules, each one of which includes its own internal clock, one of the plurality of processor modules is designated as a master processor module having a master internal clock. Each other processor module is designated as a slave processor module having a slave processor module internal clock. Each slave processor module synchronizes its internal clock with the master internal clock.

Claims

1. In a multiprocessor system comprising a plurality of processor modules, each one of the plurality of processor modules comprising an internal clock, a method for maintaining a substantially consistent running clock for the multiprocessor system, the method comprising:

(a) designating one processor module to be a master processor module having a master internal clock;

(b) designating each other processor module to be a slave processor module having a slave processor module internal clock; and

(c) synchronizing each slave processor module internal clock by, for each slave processor module,

(i) requesting, by the slave processor module at a first time according to the slave processor module internal clock, a current time according to the master internal clock;

(ii) receiving, by the slave processor module at a second time according to the slave processor module internal clock, the current time according to the master internal clock;

(iii) computing, by the slave processor module, an expected time by using at least the first time according to the slave processor module internal clock and the second time according to the slave processor module internal clock;

(iv) determining, by the slave processor module, whether the expected time differs from the received current time according to the master internal clock; and

(v) upon determining that the expected time differs from the received current time according to the master internal clock, correcting, by the slave processor module, the slave processor module internal clock.

2. The method of claim 1, wherein step (c) further comprises determining, by the slave processor module after completing sub-steps (i) and (ii) but before completing sub-steps (iii), (iv), and (v), whether the first time according to the slave processor module internal clock differs from the second time according to the slave processor module internal clock by less than a pre-determined amount.

3. The method of claim 2, wherein sub-steps (iii), (iv), and (v) of step (c) are performed upon the slave processor module determining that the first time according to the slave processor module internal clock differs from the second time according to the slave processor module internal clock by less than the pre-determined amount.

4. The method of claim 1, wherein computing the expected time comprises computing a round trip time, wherein the round trip time is computed by subtracting the first time according to the slave processor module internal clock from the second time according to the slave processor module internal clock.

5. The method of claim 4, wherein computing the expected time further comprises computing the sum of the first time according to the slave processor module internal clock and one half the round trip time.

6. The method of claim 1, wherein determining whether the expected time differs from the received current time according to the master internal clock comprises determining whether the expected time differs from the received current time according to the master internal clock by more than a pre-determined amount.

7. The method of claim 6, wherein sub-step (v) of step (c) is only performed when the slave processor module determines that the expected time differs from the received current time according to the master internal clock by more than the pre-determined amount.

8. The method of claim 6, wherein, upon determining that the expected time is greater than the received current time according to the master internal clock by more than the pre-determined amount, correcting the slave processor module internal clock comprises slowing down the slave processor module internal clock.

9. The method of claim 8, wherein the multiprocessor system comprises a free-running counter, and wherein slowing down the slave processor module internal clock comprises increasing the number of counts that the slave processor module uses in a given time interval.

10. The method of claim 6, wherein, upon determining that the received current time according to the master internal clock is greater than the expected time by more than the pre-determined amount, correcting the slave processor module internal clock comprises speeding up the slave processor module internal clock.

11. The method of claim 10, wherein the multiprocessor system comprises a free-running counter, and wherein speeding up the slave processor module internal clock comprises decreasing the number of counts that the slave processor module uses in a given time interval.

12. The method of claim 1, wherein the slave processor module internal clock is corrected such that it continually moves forwards in time.

13. The method of claim 1 further comprising periodically repeating step (c).

14. The method of claim 1, wherein the multiprocessor system is a server in a network, and further comprising receiving, by the slave processor module, a write operation.

15. The method of claim 14 further comprising acknowledging, by the slave processor module when the expected time is determined to differ from the received current time according to the master internal clock by less than a specified amount of time, the received write operation before a write is actually completed.

16. The method of claim 15, wherein the specified amount of time is one half the minimum amount of time in which a host in the network can request that the multiprocessor system process a first write operation, thereafter receive an acknowledgement of the request from the multiprocessor system, and thereafter request that the multiprocessor system process a second write operation.

17. The method of claim 14 further comprising refraining from acknowledging, by the slave processor module when the expected time is determined to differ from the received current time by more than a specified amount of time, the received write operation.

18. The method of claim 17, wherein the specified amount of time is one half the minimum amount of time in which a host in the network can request that the multiprocessor system process a first write operation, thereafter receive an acknowledgement of the request from the multiprocessor system, and thereafter request that the multiprocessor system process a second write operation.

19. The method of claim 1 further comprising maintaining, by the master processor module, a table that relates the master internal clock to a real world clock.

20. The method of claim 1, wherein the current time according to the master internal clock is requested by the slave processor module in a packet.

21. The method of claim 1, wherein the current time according to the master internal clock is received by the slave processor module in a packet.

22. A multiprocessor system for maintaining a substantially consistent running clock, comprising:

a master processor module comprising a master internal clock; and

at least one slave processor module comprising a slave processor module internal clock, the at least one slave processor module configured to;

(a) request, at a first time according to the slave processor module internal clock, a current time according to the master internal clock;

(b) receive, at a second time according to the slave processor module internal clock, the current time according to the master internal clock;

(c) compute an expected time by using at least the first time according to the slave processor module internal clock and the second time according to the slave processor module internal clock;

(d) determine whether the expected time differs from the received current time according to the master internal clock; and

(e) correct, upon determining that the expected time differs from the received current time according to the master internal clock, the slave processor module internal clock.