Real time clock architecture and/or method for a system on a chip (SOC) application

• US 20060047991A1
• Filed: 08/27/2004
• Published: 03/02/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Leung, Ho-Ming, Toth, Zoltan, Hung, Eric, Perrin, Daniel S., Lenoir, Remi C., Wilson, Timothy J.
• Granted Patent: US 7,340,634 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Claims

1. An apparatus comprising:

a first portion configured to generate a count signal in response to a number of oscillations of a clock signal, wherein said first portion is powered by an unswitched power source;

a second portion configured to generate an interrupt signal in response to said count signal and a predetermined stored value, wherein said second portion is powered by a switched power source; and

a processor configured to (i) receive said interrupt signal and (ii) generate said switched power.

2. The apparatus according to claim 1, wherein said first portion comprises hardware and said second portion comprises software.

3. The apparatus according to claim 1, wherein said first portion comprises:

an oscillator circuit connected to a crystal; and

a counter circuit connected to said oscillator circuit, wherein said counter circuit is configured to generate said count signal.

4. The apparatus according to claim 2, wherein said counter comprises an asynchronous counter.

5. The apparatus according to claim 3, wherein said asynchronous counter comprises a multi-bit counter.

6. The apparatus according to claim 1, wherein said second portion comprises:

a register configured to generate said predetermined stored value; and

a comparator configured to generate said interrupt signal.

7. The apparatus according to claim 1, wherein said clock signal is used to clock a system on a chip circuit.

8. The apparatus according to claim 1, wherein said apparatus further comprises a comparator configured to compare said switched power to said unswitched power to determine if a power source supplying said unswitched power is running low.

9. The apparatus according to claim 8, wherein said unswitched power is generated using a battery.

10. The apparatus according to claim 3, wherein said counter is implemented without setting said counter.

11. The apparatus according to claim 1, wherein said apparatus uses a difference between said count signal and a real time clock to determine a real time value.

12. The apparatus according to claim 1, wherein said real time value is used by a system on a chip circuit to initiate timed events.

13. The apparatus according to claim 11, wherein said real time clock is calculated using software.

14. An apparatus comprising:

means for generating a count signal in response to a number of oscillations of a clock signal, wherein said first portion is powered by an unswitched power source;

means for generating an interrupt signal in response to said count signal and a predetermined stored value, wherein said second portion is powered by a switched power source; and

means for (i) receiving said interrupt signal and (ii) generating said switched power.

15. A method for generating a clock signal comprising the steps of:

(A) generating a count signal in response to a number of oscillations of said clock signal, wherein step (A) generates said count signal while powered by an unswitched power source;

(B) generating an interrupt signal in response to said count signal and a predetermined stored value, wherein step (B) generates said interrupt signal while powered by a switched power source; and

(C) receiving said interrupt signal and generating said switched power.