Methods and apparatus for optimally selecting a storage buffer for the storage of data

• US 20060047998A1
• Filed: 08/24/2004
• Published: 03/02/2006
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Veritas Technologies, LLC (Whitehouse Group Ltd.)
• Original Assignee: Symantec Operating Corporation (NortonLifeLock Inc.)
• Inventors: Darcy, Jeff
• Granted Patent: US 7,631,120 B2
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/1464 for networked environments
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A storage management device can receive a write operation that includes a data payload, store a first instance of the data payload at a first storage buffer in the storage management device, and evaluate a first cost equation to identify a second storage buffer in the storage management device, different from the first storage buffer, at which to optimally store a second instance of the data payload.

Claims

1. In a device comprising a first processor module and a plurality of storage buffers, a method for storing data, the method comprising:

receiving, at the first processor module, a write operation comprising a data payload;

storing, by the first processor module, at a first storage buffer on the first processor module a first instance of the data payload; and

evaluating, by the first processor module, a first cost equation to identify a second storage buffer, different from the first storage buffer, from amongst the plurality of storage buffers at which to optimally store a second instance of the data payload.

2. The method of claim 1 further comprising evaluating, by the first processor module, a second cost equation to identify a third storage buffer, different from the first and second storage buffers, from amongst the plurality of storage buffers at which to optimally store a third instance of the data payload.

3. The method of claim 1, wherein evaluating the first cost equation to identify the second storage buffer comprises assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to a physical distance in the device from the first processor module to that one of the plurality of storage buffers.

4. The method of claim 1, wherein evaluating the first cost equation to identify the second storage buffer comprises assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to an available capacity of that one of the plurality of storage buffers.

5. The method of claim 1, wherein the device further comprises at least one second processor module comprising at least one of the plurality of storage buffers, different from the first storage buffer, and wherein evaluating the first cost equation to identify the second storage buffer comprises assigning, for each second processor module, a value to a load present at that second processor module.

6. The method of claim 5, wherein the load present at each second processor module comprises an input/output load.

7. The method of claim 5, wherein the load present at each second processor module comprises an interconnect load between that second processor module and at least one other processor module.

8. The method of claim 1, wherein the device further comprises at least one second processor module, and wherein evaluating the first cost equation to identify the second storage buffer comprises assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to the number of processor modules that would be able to access at least one of the first instance and the second instance of the data payload if the second instance of the data payload were stored at that one of the plurality of storage buffers.

9. The method of claim 1 further comprising separating, by the first processor module, the data payload from the write operation to create the first instance of the data payload, and replicating, by the first processor module, the first instance of the data payload to create the second instance of the data payload.

10. The method of claim 1 further comprising transmitting from the first processor module to the second storage buffer, the second instance of the data payload.

11. The method of claim 1 further comprising storing the second instance of the data payload at the second storage buffer.

12. The method of claim 1, wherein the device further comprises a second processor module different from the first processor module, and wherein the second storage buffer is located on the second processor module.

13. The method of claim 1, wherein the device comprises memory and wherein at least one of the plurality of storage buffers is contained within the memory.

14. A device for storing data, comprising:

a plurality of storage buffers; and

a first processor module, comprising;

a receiver for receiving a write operation comprising a data payload;

a first storage buffer from amongst the plurality of storage buffers for storing a first instance of the data payload; and

an evaluator for evaluating a first cost equation to identify a second storage buffer, different from the first storage buffer, from amongst the plurality of storage buffers at which to optimally store a second instance of the data payload.

15. The device of claim 14, wherein the evaluator is capable of evaluating a second cost equation to identify a third storage buffer, different from the first and second storage buffers, from amongst the plurality of storage buffers at which to optimally store a third instance of the data payload.

16. The device of claim 14, wherein the evaluator, in evaluating the first cost equation to identify the second storage buffer, is capable of assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to a physical distance in the device from the first processor module to that one of the plurality of storage buffers.

17. The device of claim 14, wherein the evaluator, in evaluating the first cost equation to identify the second storage buffer, is capable of assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to an available capacity of that one of the plurality of storage buffers.

18. The device of claim 14 further comprising at least one second processor module.

19. The device of claim 18, wherein the at least one second processor module comprises at least one of the plurality of storage buffers, different from the first storage buffer.

20. The device of claim 19, wherein the evaluator, in evaluating the first cost equation to identify the second storage buffer, is capable of assigning, for each second processor module, a value to a load present at that second processor module.

21. The device of claim 20, wherein the load present at each second processor module comprises an input/output load.

22. The device of claim 20, wherein the load present at each second processor module comprises an interconnect load between that second processor module and at least one other processor module.

23. The device of claim 18, wherein the evaluator, in evaluating the first cost equation to identify the second storage buffer, is capable of assigning, for each one of the plurality of storage buffers other than the first storage buffer, a value to the number of processor modules that would be able to access at least one of the first instance and the second instance of the data payload if the second instance of the data payload were stored at that one of the plurality of storage buffers.

24. The device of claim 14, wherein the first processor module further comprises a data operator for separating the data payload from the write operation to create the first instance of the data payload, and for replicating the first instance of the data payload to create the second instance of the data payload.

25. The device of claim 14, wherein the first processor module further comprises a transmitter for transmitting, to the second storage buffer, the second instance of the data payload.

26. The device of claim 14 further comprising a second processor module, different from the first processor module, comprising the second storage buffer.

27. The device of claim 14 further comprising memory and wherein at least one of the plurality of storage buffers is contained within the memory.