Method and system for performing timing analysis on a circuit
First Claim
1. A method of analyzing a circuit, said circuit comprising at least two nodes, each of said at least two nodes have timing requirements associated therewith, said method comprising:
- receiving a failure time of first node, wherein said failure time represents the time within which a signal must arrive at said first node from said second node in order to avoid a timing violation of said circuit, said second node being upstream of said first node;
determining a potential slack for said first node based on said failure time of said first node, wherein said potential slack is equal to said failure time minus the sum of said target time and the delay between said first node and said second node;
terminating said analysis if said potential slack is less than a first predetermined value;
determining the target slack at said first node, wherein said target slack is equal to said timing requirement of said first node minus the sum of said timing requirement of said second node and the delay between said first node and said second node; and
changing the timing requirement of said first node if said target slack is less than a second predetermined value.
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Abstract
A method and apparatus for analyzing a circuit are described herein. The circuit may comprise at least two nodes, wherein each of the nodes has timing requirements associated therewith. An embodiment of the method comprises receiving a failure time of first node, wherein the failure time represents the time within which a signal must arrive at the first node from the second node in order to avoid a timing violation of the circuit. The second node is upstream of the first node. A potential slack is determined for the first node based on the failure time of the first node, wherein the potential slack is equal to the failure time minus the sum of the target time and the delay between the first node and the second node. The analysis is terminated if the potential slack is less than a first predetermined value. The target slack at the first node is determined, wherein the target slack is equal to the timing requirement of the first node minus the sum of the timing requirement of the second node and the delay between the first node and the second node. The timing requirement of the first node may be changed or relaxed if the target slack is less than a second predetermined value.
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Citations
20 Claims
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1. A method of analyzing a circuit, said circuit comprising at least two nodes, each of said at least two nodes have timing requirements associated therewith, said method comprising:
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receiving a failure time of first node, wherein said failure time represents the time within which a signal must arrive at said first node from said second node in order to avoid a timing violation of said circuit, said second node being upstream of said first node;
determining a potential slack for said first node based on said failure time of said first node, wherein said potential slack is equal to said failure time minus the sum of said target time and the delay between said first node and said second node;
terminating said analysis if said potential slack is less than a first predetermined value;
determining the target slack at said first node, wherein said target slack is equal to said timing requirement of said first node minus the sum of said timing requirement of said second node and the delay between said first node and said second node; and
changing the timing requirement of said first node if said target slack is less than a second predetermined value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of analyzing a circuit, said circuit comprising at least one circuit block and a plurality of nodes, said method comprising:
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creating a directed acyclic graph representative of said circuit;
creating a topological sort from said directed acyclic graph list that includes said plurality of nodes;
initializing the plurality of nodes to indicate that they have not been analyzed, wherein said analyzing comprises determining target slack and potential slack at said nodes;
obtaining data representative of timing requirements associated with a first node from said topological sort list;
changing said timing requirement associated with said first node;
determining whether said first node has been analyzed;
analyzing said first node if said first node has not been analyzed, the analyzing comprising;
determining a potential slack of said first node, wherein said potential slack is equal to a failure time associated with said first node minus the sum of a target time associated with said first node and the delay between said first node and a second node, said second node being upstream of said first node;
terminating said analyzing if said potential slack is less than a preselected value; and
determining the target slack at said first node, wherein said target slack is equal to said timing requirement of said first node minus the sum of said timing requirement of said second node and the delay between said first node and said second node;
saving said change to said timing target if said target slack is in a less than a predetermined value. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An apparatus for analyzing a circuit, said circuit comprising at least two nodes, wherein each of said at least two nodes have timing requirements associated therewith, said apparatus comprising:
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at least one computer readable medium; and
computer readable program code stored on said at least one computer readable medium, said computer readable program code comprising instructions for;
receiving a failure time of first node, wherein said failure time represents the time within which a signal must arrive at said first node from said second node in order to avoid a timing violation of said circuit, said second node being upstream of said first node;
determining a potential slack for said first node based on said failure time of said first node, wherein said potential slack is equal to said failure time minus the sum of said target time and the delay between said first node and said second node;
terminating said analysis if said potential slack is less than a first predetermined value;
determine the target slack at said first node, wherein said target slack is equal to said timing requirement of said first node minus the sum of said timing requirement of said second node and the delay between said first node and said second node; and
changing the timing requirement of said first node if said target slack is less than a second predetermined value. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification