Forming ferroelectric polymer memories

• US 20060048376A1
• Filed: 10/31/2005
• Published: 03/09/2006
• Est. Priority Date: 05/31/2002
• Status: Abandoned Application

• Current Assignee: Ebrahim Andideh, Mani Rahnama, Mark Isenberger, Michael Leeson
• Original Assignee: Ebrahim Andideh, Mani Rahnama, Mark Isenberger, Michael Leeson
• Inventors: Andideh, Ebrahim, Rahnama, Mani, Leeson, Michael, Isenberger, Mark
• Application Number:
  US11/263,629
• Publication Number:
  US 20060048376A1
• Time in Patent Office: Days
• US Class Current: 29/604
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: Y10T 29/49069 Data storage inductor or core
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.

Claims

1. A method comprising:

coating a first metal layer with hexamethyldisilazane;

forming a layer of polymer over said coating, said polymer to act as a ferroelectric polymer in a ferroelectric polymer memory; and

plasma etching a second metal layer formed over said polymer using a gas mixture including helium, said metal layers and polymer layer to form a first layer of ferroelectric polymer memory.

2. The method of claim 1 including forming a polyimide layer over said first layer of ferroelectric polymer memory.

3. The method of claim 2 including forming a second layer of a ferroelectric polymer memory and forming another polyimide layer over said second memory layer.

4. The method of claim 1 wherein forming a layer of polymer over said coating includes forming a copolymer layer including vinyledene fluoride and trifloroethylene over said coating.

5. The method of claim 4 including spin coating the copolymer in an organic solvent.

6. The method of claim 5 including evaporating the organic solvent using heat.

7. The method of claim 1 wherein plasma etching a second metal layer includes etching said metal layer with a selectivity greater then 1.25.

8. The method of claim 1 wherein plasma etching a second metal layer includes etching said metal layer with a selectivity greater than 2.

9. The method of claim 1 wherein plasma etching a second metal layer includes using a radio frequency bias from about 20 to about 30 Watts.

10. The method of claim 1 wherein plasma etching a second metal layer includes using a gas mixture including Cl₂ and BCL₃.

11. A method comprising:

forming a ferroelectric polymer over a first metal layer, said first metal layer patterned to form metal bitlines, said ferroelectric polymer to extend over said bitlines and downward between said bitlines toward an underlying substrate; and

forming a second metal layer over said ferroelectric polymer layer, said second metal layer to be patterned to form row lines that extend transverse to said bitlines.

12. The method of claim 11 wherein forming a ferroelectric polymer over a first metal layer includes forming a ferroelectric copolymer of vinyledene fluoride and trifluoroethylene over said first metal layer.

13. The method of claim 11 further including before forming said ferroelectric polymer, coating said bitlines with hexamethyldisilazane.

14. The method of claim 13 further including using a solution including diethylcarbonate to coat said bitlines.

15. The method of claim 13 further including annealing to form a piezoelectric film.

16. The method of claim 11 wherein said first and second metal layers and said ferroelectric polymer form a first layer of a ferroelectric polymer memory.

17. The method of claim 16 further including forming a polyimide layer over said metal row lines.

18. The method of claim 17 further including forming a second layer of ferroelectric polymer memory over said polyimide layer, said second layer of ferroelectric polymer memory including a ferroelectric polymer formed over metal bitlines and metal row lines formed over said ferroelectric polymer.

19. The method of claim 18 including forming another polyimide layer over said second layer of ferroelectric polymer memory.

20. A method comprising:

forming a layer of a polymer over a first metal layer coated with hexamethyldisilazane, said polymer to enable data storage in a ferroelectric polymer memory;

plasma etching a second metal layer formed over said polymer, said plasma etching using a gas mixture including helium; and

after said etching, forming a polyimide layer over said second metal layer.

23. The method of claim 20 including etching said second metal layer with a selectivity greater than 2.

24. The method of claim 20 wherein plasma etching includes plasma etching using a radio frequency bias of from about 20 Watts to about 30 Watts.

25. The method of claim 20 wherein plasma etching includes plasma etching using a gas mixture including Cl₂ and BCL₃.

26. The method of claim 20 wherein forming a layer of a polymer includes forming a copolymer including vinyledene fluoride and trifluroethylene.

27. The method of claim 20 wherein said polymer and said first and second metal layers form a first layer of a ferroelectric polymer memory, and including forming a second layer of ferroelectric polymer memory over said polyimide layer, the polymer layer of the second layer of ferroelectric polymer memory formed;

over a metal layer, and a hexamethyldisilazane layer between said polymer layer and said metal layer of said second layer of ferroelectric polymer memory.

21. The method of claim 21 including forming a plurality of bitlines over a semiconductor structure.

22. The method of claim 21 wherein plasma etching includes etching a plurality of row lines extending generally transverse to said bitlines.