Barrier regions for image sensors

• US 20060049432A1
• Filed: 11/01/2005
• Published: 03/09/2006
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Mauritzson, Richard A., Rhodes, Howard E., Quinlin, William T.
• Granted Patent: US 7,772,027 B2
• Time in Patent Office: Days
• US Class Current: 257/234
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Embodiments of the invention provide a barrier region for isolating devices of an image sensor. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region is adjacent to at least one pixel cell of a pixel array. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Claims

1-53. -53. (canceled)

54. A method of forming a barrier region for isolating devices of an image sensor, the method comprising:

forming a charge accumulation region having a particular conductivity type in a substrate adjacent to at least one pixel cell; and

electrically connecting the charge accumulation region to a voltage source terminal.

55. The method of claim 54, wherein the act of forming the charge accumulation region comprises forming an np diode.

56. The method of claim 54, wherein the act of forming the charge accumulation region comprises forming a pnp diode.

57. The method of claim 54, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with n-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a positive voltage source terminal.

58. The method of claim 57, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 5×

10¹¹ to approximately 1×

10¹⁴ atoms/cm².

59. The method of claim 57, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 2×

10¹² atoms/cm² to approximately 1×

10¹⁴ atoms/cm².

60. The method of claim 57, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

61. The method of claim 54, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with p-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a ground voltage source terminal.

62. The method of claim 54, wherein the act of connecting the charge accumulation region to a voltage source terminal comprises forming a contact and a metal connection.

63. The method of claim 62, further comprising forming a contact region of the particular conductivity type below the contact.

64. The method of claim 63, wherein the act of forming the contact region comprises forming the contact region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

65. The method of claim 54, wherein the act of forming the barrier region comprises forming the barrier region as at least a portion of a pixel cell in the array.

66. The method of claim 54, wherein the act of forming the barrier region comprises forming the barrier region as a group of pixel cells in the array, and wherein the act of forming the charge accumulation region comprises forming a continuous charge accumulation region.

67. The method of claim 66, wherein the act of forming the barrier region comprises forming the barrier region as a row of pixel cells.

68. The method of claim 66, wherein the act of forming the barrier region comprises forming the barrier region as a column of pixel cells.

69. A method of forming an image sensor, the method comprising:

providing a substrate;

providing an array of pixel cells on the substrate; and

forming at least one barrier region adjacent to at least one pixel cell by forming a charge accumulation region of a particular conductivity type on the substrate and electrically connecting the charge accumulation region to a voltage source terminal.

70. The method of claim 69, wherein the act of forming the charge accumulation region comprises forming an np diode.

71. The method of claim 69, wherein the act of forming the charge accumulation region comprises forming a pnp diode.

72. The method of claim 69, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with n-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a positive voltage source terminal.

73. The method of claim 72, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 5×

10¹¹ to approximately 1×

10¹⁴ atoms/cm².

74. The method of claim 72, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 2×

10¹² atoms/cm² to approximately 1×

10¹⁴ atoms/cm².

75. The method of claim 72, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

76. The method of claim 69, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with p-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a ground voltage source terminal.

77. The method of claim 69, wherein the act of connecting the charge accumulation region to a voltage source terminal comprises forming a contact and a metal connection.

78. The method of claim 77, the act of forming the barrier region comprises forming a contact region of the particular conductivity type below the contact.

79. The method of claim 78, wherein the act of forming the contact region comprises forming the contact region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

80. The method of claim 69, further comprising peripheral circuitry adjacent to the array, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region between the array and the peripheral circuitry.

81. The method of claim 69, wherein the act of providing the array comprises providing the array comprising an active array region comprising a first portion of pixel cells, and at least one black region comprising a second portion of pixel cells not in the active array region, and wherein the act of forming the at least one barrier region comprises forming the at least one barrier region between the active array region and the at least one black region.

82. The method of claim 81, wherein the act of providing the array comprises providing the array comprising a first black region adjacent to a first side of the active array region and at least a second black region adjacent to a second side of the active array region, the first and at least second black regions for determining the black level of the array, and wherein the act of forming the at least one barrier region comprises forming the at least one barrier region between the first black region and the active array region and between the at least second black region and the active array region.

83. The method of claim 81, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region surrounding the active array region.

84. The method of claim 81, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region surrounding the at least one black region.

85. The method of claim 69, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region surrounding the array.

86. The method of claim 69, further comprising forming a plurality of barrier regions.

87. The method of claim 69, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as at least a portion of a pixel cell in the array.

88. The method of claim 69, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a group of pixel cells in the array and forming a continuous charge accumulation region.

89. The method of claim 88, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a row of pixel cells.

90. The method of claim 88, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a column of pixel cells.

91. The method of claim 69, wherein the act of forming the at least one barrier region further comprises forming at least one transistor.

92. The method of claim 69, further comprising forming a light blocking layer, the light blocking layer being formed of a material from of:

metal, an opaque color filter array material, an opaque organic material, and an opaque inorganic material.

93. A method of forming an image sensor, the method comprising:

providing an array of pixel cells on a substrate;

providing peripheral circuitry adjacent to the array; and

forming a plurality of barrier regions by forming a plurality of n-type charge accumulation regions on the substrate and electrically connecting each of the charge accumulation regions to a positive voltage source terminal, each barrier region being formed adjacent to at least one pixel cell.

94. The method of claim 93, wherein the act of forming the plurality of barrier regions comprises forming a first portion of the barrier regions between the array and the peripheral circuitry and forming a second portion of the barrier regions between two or more pixel cells.

95. The method of claim 93, wherein the act of forming the plurality of barrier regions comprises forming one or more of the barrier regions as at least a portion of a pixel cell in the array.