CMOS image sensors and methods for fabricating the same

• US 20060049437A1
• Filed: 12/29/2004
• Published: 03/09/2006
• Est. Priority Date: 09/06/2004
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Hwang, Joon
• Application Number:
  US11/026,182
• Publication Number:
  US 20060049437A1
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Complementary metal-oxide semiconductor (CMOS) image sensors and methods of fabricating the same are disclosed. In one example, the method includes forming at least a first pad layer and a second pad layer on a p-type semiconductor substrate having an active area and a device dividing area defined thereon, removing the first pad layer and the second pad layer on the device dividing area, so as to expose the p-type semiconductor layer and selectively removing the exposed p-type semiconductor layer, thereby forming a trench, forming a first p-type impurity area on a portion of the p-type semiconductor substrate formed on inner walls of the trench, forming a device dividing insulating layer on an entire surface of the p-type semiconductor substrate so as to fill the trench, removing the device dividing insulating layer, so that the device dividing insulating layer remains only in the trench, and removing the second pad layer, and injecting n-type impurity ions onto the active area, thereby forming a photodiode area.

Claims

1. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:

a semiconductor substrate having a device dividing area and an active area defined thereon;

a photodiode having the active area of the semiconductor substrate covered by a p-type impurity area and generating optical electric charges in accordance with a luminance of a light; and

color filter layers and micro-lenses formed on a vertical line of the photodiode.

3. A CMOS image sensor as defined by claim 1, wherein the device dividing layer is formed of a high density plasma (HPD) oxide layer.

2. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:

a semiconductor substrate having a device dividing area and an active area defined thereon;

a trench formed on the device dividing area of the semiconductor substrate;

a first p-type impurity area formed on inner walls of the trench;

a device dividing layer formed on the active area adjacent to the first p-type impurity area;

a second p-type impurity area formed on a surface of the photodiode area; and

color filter layers and micro-lenses formed on a vertical line of the photodiode.

4. A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor, comprising:

forming at least a first pad layer and a second pad layer on a p-type semiconductor substrate having an active area and a device dividing area defined thereon;

removing the first pad layer and the second pad layer on the device dividing area, so as to expose the p-type semiconductor layer and selectively removing the exposed p-type semiconductor layer, thereby forming a trench;

forming a first p-type impurity area on a portion of the p-type semiconductor substrate formed on inner walls of the trench;

forming a device dividing insulating layer on an entire surface of the p-type semiconductor substrate so as to fill the trench;

removing the device dividing insulating layer, so that the device dividing insulating layer remains only in the trench, and removing the second pad layer; and

injecting n-type impurity ions onto the active area, thereby forming a photodiode area.

5. A method as defined by claim 4, wherein the first pad layer is formed of an oxide layer, and wherein the second pad layer is formed of an oxide layer, or a nitride layer, and a tetra ethyl ortho silicate (TEOS) oxide layer deposited thereon.

6. A method as defined by claim 4, further comprising, before forming a first p-type impurity area on a portion of the p-type semiconductor substrate formed on inner walls of the trench, forming a sacrifice oxide layer on inner walls of the trench.

7. A method as defined by claim 6, wherein the sacrifice oxide layer is formed by using a heat oxidation process.

8. A method as defined by claim 4, wherein the first p-type impurity area is formed by injecting p-type impurity ions using a tilted ion injection method.

9. A method as defined by claim 4, wherein the device dividing insulating layer is formed of a high density plasma (HDP) oxide layer.

10. A method as defined by claim 4, wherein the device dividing insulating layer and the second pad layer are removed by using a chemical mechanical polishing (CMP) process.

11. A method as defined by claim 4, further comprising forming a first p-type impurity area on a surface of the photodiode area.

12. A method as defined by claim 4, further comprising:

forming a gate insulating layer and a gate electrode on the p-type semiconductor substrate;

forming a source/drain area; and

forming color filter layers and micro-lenses on an upper surface of the photodiode area.