Image sensor with on-chip semi-column-parallel pipeline ADCS

• US 20060050162A1
• Filed: 10/05/2004
• Published: 03/09/2006
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Nakamura, Junichi
• Granted Patent: US 7,570,293 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

Claims

1. An imaging device comprising:

an array of pixels organized into a plurality of rows and columns;

a plurality of sample and hold circuits, each circuit being electrically connected to a respective column of said array, each circuit sampling and holding analog signals from the respective column; and

a plurality of pipeline analog-to-digital converters, each pipeline analog-to-digital converter being electrically connected to a respective number of sample and hold circuits, each analog-to-digital converter converting the held analog signals from the respective number of sample and hold circuits into digital data.

2. The device of claim 1, wherein each pipeline analog-to-digital converter is connected to more than one sample and hold circuit.

3. The device of claim 1, wherein each pipeline analog-to-digital converter is connected to twelve sample and hold circuits.

4. The device of claim 1, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein the number of pipeline stages is equal to the number of sample and hold circuits said analog-to-digital converter is connected to.

5. The device of claim 1 further comprising:

a first memory bank connected to said analog-to-digital converters, said first memory bank storing digital data from all of the analog-to-digital converters;

a second memory bank connected to said first memory bank, said second memory bank inputting and storing the stored digital data from the first memory bank; and

a column scanner connected to said memory bank, said column scanner controlling the second memory bank to output the digital data stored in said second memory bank.

6. The device of claim 5, further comprising:

a first set of switches connected between said sample and hold circuits and said analog-to-digital converters;

a second set of switches connected between said analog-to-digital converters and said first memory bank;

a third set of switches between said first and second memory banks; and

a fourth set of switches between said second memory bank and said scanner.

7. The device of claim 6 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations do not occur when analog-to-digital conversions and data readout operations occur.

8. The device of claim 6 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations, analog-to-digital conversions and data readout operations occur during a same time period.

9. The device of claim 1, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein each pipeline stage comprises:

a pipeline stage sample and hold circuit connected to input, sample and hold the analog signals;

a k-bit analog-to-digital converter circuit connected to receive the analog signals from the pipeline stage sample and hold circuit, said k-bit analog-to-digital converter circuit creating k-bit digital data from the analog signals;

a k-bit digital-to-analog converter circuit connected to receive the k-bit digital data from the k-bit analog-to-digital converter circuit, said k-bit digital-to-analog converter circuit creating analog signals from the k-bit digital data;

a subtractor connected to receive the analog signals from the k-bit digital-to-analog converter circuit and the analog signals from the pipeline stage sample and hold circuit, said subtractor generating a difference output; and

an amplifier for amplifying the difference output.

10. The device of claim 9, wherein k-bit is the digital resolution of the plurality of analog-to-digital converters.

11. The device of claim 1, wherein said array comprises CMOS imager pixels.

12. An imaging device comprising:

an array of pixels organized into a plurality of rows and columns;

a plurality of sample and hold circuits, each circuit being electrically connected to a respective column of said array, each circuit sampling and holding analog signals from the respective column; and

a plurality of pipeline analog-to-digital converters, each pipeline analog-to-digital converter being electrically connected to the sample and hold circuits in a semi-column-parallel manner, each analog-to-digital converter converting the held analog signals from the respective number of sample and hold circuits into digital data.

13. The device of claim 12, wherein each pipeline analog-to-digital converter is connected to more than one sample and hold circuit.

14. The device of claim 12, wherein each pipeline analog-to-digital converter is connected to twelve sample and hold circuits.

15. The device of claim 12, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein the number of pipeline stages is equal to a number of sample and hold circuits said analog-to-digital converter is connected to.

16. The device of claim 12 further comprising:

a first memory bank connected to said analog-to-digital converters, said first memory bank storing digital data from all of the analog-to-digital converters;

a second memory bank connected to said first memory bank, said second memory bank inputting and storing the stored digital data from the first memory bank; and

a column scanner connected to said memory bank, said column scanner controlling the second memory bank to output the digital data stored in said second memory bank.

17. The device of claim 16, further comprising:

a first set of switches connected between said sample and hold circuits and said analog-to-digital converters;

a second set of switches connected between said analog-to-digital converters and said first memory bank;

a third set of switches between said first and second memory banks; and

a fourth set of switches between said second memory bank and said scanner.

18. The device of claim 17 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations do not occur when analog-to-digital conversions and data readout operations occur.

19. The device of claim 17 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations, analog-to-digital conversions and data readout operations occur during a same time period.

20. The device of claim 12, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein each pipeline stage comprises:

a pipeline stage sample and hold circuit connected to input, sample and hold the analog signals;

a k-bit analog-to-digital converter circuit connected to receive the analog signals from the pipeline stage sample and hold circuit, said k-bit analog-to-digital converter circuit creating k-bit digital data from the analog signals;

a k-bit digital-to-analog converter circuit connected to receive the k-bit digital data from the k-bit analog-to-digital converter circuit, said k-bit digital-to-analog converter circuit creating analog signals from the k-bit digital data;

a subtractor connected to receive the analog signals from the k-bit digital-to-analog converter circuit and the analog signals from the pipeline stage sample and hold circuit, said subtractor generating a difference output; and

an amplifier for amplifying the difference output.

21. The device of claim 20, wherein k-bit is the digital resolution of the plurality of analog-to-digital converters.

22. The device of claim 12, wherein said array comprises CMOS imager pixels.

23. A processor system comprising:

a processor; and

an imaging device connected to said processor, said imaging device comprising;

an array of pixels organized into a plurality of rows and columns;

a plurality of sample and hold circuits, each circuit being electrically connected to a respective column of said array, each circuit sampling and holding analog signals from the respective column; and

a plurality of pipeline analog-to-digital converters, each pipeline analog-to-digital converter being electrically connected to a respective number of sample and hold circuits, each analog-to-digital converter converting the held analog signals from the respective number of sample and hold circuits into digital data.

24. The system of claim 23, wherein each pipeline analog-to-digital converter is connected to more than one sample and hold circuit.

25. The system of claim 23, wherein each pipeline analog-to-digital converter is connected to twelve sample and hold circuits.

26. The system of claim 23, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein the number of pipeline stages is equal to the number of sample and hold circuits said analog-to-digital converter is connected to.

27. The system of claim 23 further comprising:

a first memory bank connected to said analog-to-digital converters, said first memory bank storing digital data from all of the analog-to-digital converters;

a second memory bank connected to said first memory bank, said second memory bank inputting and storing the stored digital data from the first memory bank; and

a column scanner connected to said memory bank, said column scanner controlling the second memory bank to output the digital data stored in said second memory bank.

28. The system of claim 27, further comprising:

a first set of switches connected between said sample and hold circuits and said analog-to-digital converters;

a second set of switches connected between said analog-to-digital converters and said first memory bank;

a third set of switches between said first and second memory banks; and

a fourth set of switches between said second memory bank and said scanner.

29. The system of claim 28 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations do not occur when analog-to-digital conversions and data readout operations occur.

30. The system of claim 28 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations, analog-to-digital conversions and data readout operations occur during a same time period.

31. The system of claim 23, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein each pipeline stage comprises:

a pipeline stage sample and hold circuit connected to input, sample and hold the analog signals;

a k-bit analog-to-digital converter circuit connected to receive the analog signals from the pipeline stage sample and hold circuit, said k-bit analog-to-digital converter circuit creating k-bit digital data from the analog signals;

a k-bit digital-to-analog converter circuit connected to receive the k-bit digital data from the k-bit analog-to-digital converter circuit, said k-bit digital-to-analog converter circuit creating analog signals from the k-bit digital data;

a subtractor connected to receive the analog signals from the k-bit digital-to-analog converter circuit and the analog signals from the pipeline stage sample and hold circuit, said subtractor generating a difference output; and

an amplifier for amplifying the difference output.

32. The system of claim 31, wherein k-bit is the digital resolution of the plurality of analog-to-digital converters.

33. The system of claim 23, wherein said array comprises CMOS imager pixels.

34. A processor system comprising:

a processor; and

an imaging device connected to said processor, said imaging device comprising;

an array of pixels organized into a plurality of rows and columns;

a plurality of sample and hold circuits, each circuit being electrically connected to a respective column of said array, each circuit sampling and holding analog signals from the respective column; and

a plurality of pipeline analog-to-digital converters, each pipeline analog-to-digital converter being electrically connected to the sample and hold circuits in a semi-column-parallel manner, each analog-to-digital converter converting the held analog signals from the respective number of sample and hold circuits into digital data.

35. The system of claim 34, wherein each pipeline analog-to-digital converter is connected to more than one sample and hold circuit.

36. The system of claim 34, wherein each pipeline analog-to-digital converter is connected to twelve sample and hold circuits.

37. The system of claim 34, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein the number of pipeline stages is equal to a number of sample and hold circuits said analog-to-digital converter is connected to.

38. The system of claim 34 further comprising:

a first memory bank connected to said analog-to-digital converters, said first memory bank storing digital data from all of the analog-to-digital converters;

a second memory bank connected to said first memory bank, said second memory bank inputting and storing the stored digital data from the first memory bank; and

a column scanner connected to said memory bank, said column scanner controlling the second memory bank to output the digital data stored in said second memory bank.

39. The system of claim 38, further comprising:

a first set of switches connected between said sample and hold circuits and said analog-to-digital converters;

a second set of switches connected between said analog-to-digital converters and said first memory bank;

a third set of switches between said first and second memory banks; and

a fourth set of switches between said second memory bank and said scanner.

40. The system of claim 39 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations do not occur when analog-to-digital conversions and data readout operations occur.

41. The system of claim 39 further comprising at least one controller, said controller controlling the operations of said first, second, third and fourth switches such that sample and hold operations, analog-to-digital conversions and data readout operations occur during a same time period.

42. The system of claim 34, wherein each pipeline analog-to-digital converter comprises a number of pipeline stages, wherein each pipeline stage comprises:

a pipeline stage sample and hold circuit connected to input, sample and hold the analog signals;

a k-bit analog-to-digital converter circuit connected to receive the analog signals from the pipeline stage sample and hold circuit, said k-bit analog-to-digital converter circuit creating k-bit digital data from the analog signals;

a k-bit digital-to-analog converter circuit connected to receive the k-bit digital data from the k-bit analog-to-digital converter circuit, said k-bit digital-to-analog converter circuit creating analog signals from the k-bit digital data;

a subtractor connected to receive the analog signals from the k-bit digital-to-analog converter circuit and the analog signals from the pipeline stage sample and hold circuit, said subtractor generating a difference output; and

an amplifier for amplifying the difference output.

43. The system of claim 42, wherein k-bit is the digital resolution of the plurality of analog-to-digital converters.

44. The system of claim 34, wherein said array comprises CMOS imager pixels.

45. A method of constructing an imaging device, said method comprising the acts of:

forming an array of pixels organized into a plurality of rows and columns;

forming a plurality of sample and hold circuits, each circuit being electrically connected to a respective column of said array, each circuit sampling and holding analog signals from the respective column; and

forming a plurality of pipeline analog-to-digital converters, each pipeline analog-to-digital converter being electrically connected to a respective number of sample and hold circuits, each analog-to-digital converter converting the held analog signals from the respective number of sample and hold circuits into digital data.

46. A method of operating an imaging device, said method comprising the acts of:

sampling analog signals from a current row of pixels in a pixel array during a first time period;

converting the sampled analog signals into digital data during a second time period using a pipeline analog-to-digital conversion technique;

storing the digital data; and

outputting, during the second time period, previously stored digital data associated with a previous row of pixels.

47. The method of claim 46, wherein said sampling step does not occur during said converting and outputting steps.

48. The method of claim 46, wherein stored digital data associated with the current row is output during a third time period.

49. The method of claim 46, wherein the first time period corresponds to the horizontal blanking period.

50. The method of claim 46, wherein the second time period corresponds to the horizontal scanning period.

51. A method of operating an imaging device, said method comprising the acts of:

sampling analog signals from a current row of pixels in a pixel array during a first time period;

converting previously sampled analog signals into digital data during the first time period using a pipeline analog-to-digital conversion technique;

storing the digital data; and

outputting, during the first time period, previously stored digital data associated with a previous row of pixels.

52. The method of claim 51, wherein stored digital data associated with the current row is converted and then output during a subsequent time period.

53. The method of claim 51, wherein the first time period corresponds to the horizontal scanning period.