Memory system which copies successive pages, and data copy method therefor
First Claim
1. A memory system comprising:
- a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;
a first data buffer which holds, in read, data read from the memory cell array via a bit line switch and in write, data to be written in the memory cell array via the bit line switch;
a second data buffer which is configured to swap data with the first data buffer, copies data to the first data buffer, and receives a copy of data from the first data buffer;
a bus switch which is interposed between the second data buffer and a bus, selects part of data held by the second data buffer, and transfers the part of data to the bus;
an error correction circuit which is connected to the bus and performs error correction calculation of data read from the memory cell array; and
a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads, page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls to perform write in the second block in an erase state in the memory cell array.
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Accused Products
Abstract
A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.
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Citations
19 Claims
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1. A memory system comprising:
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a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;
a first data buffer which holds, in read, data read from the memory cell array via a bit line switch and in write, data to be written in the memory cell array via the bit line switch;
a second data buffer which is configured to swap data with the first data buffer, copies data to the first data buffer, and receives a copy of data from the first data buffer;
a bus switch which is interposed between the second data buffer and a bus, selects part of data held by the second data buffer, and transfers the part of data to the bus;
an error correction circuit which is connected to the bus and performs error correction calculation of data read from the memory cell array; and
a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads, page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls to perform write in the second block in an erase state in the memory cell array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory system comprising:
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a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;
a first data buffer and a second data buffer which hold, in read, data read from the memory cell array and in write, data to be written in the memory cell array;
a bit line switch which connects one of the first data buffer and the second data buffer to the memory cell array;
a bus switch which connects, to a bus, one of the first data buffer and the second data buffer that is not connected to the memory cell array;
an error correction circuit which is connected to the bus and performs error correction calculation of data read from the memory cell array; and
a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads, page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls to perform write in the second block in an erase state in the memory cell array. - View Dependent Claims (11, 12)
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13. A page copy method for a memory system, comprising:
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reading, page by page, data of a plurality of pages at successive page addresses from a memory cell array to a first data buffer;
swapping data read to the first data buffer with data of a second data buffer;
executing error correction calculation for the readout data of said plurality of pages;
correcting erroneous data detected by the error correction calculation;
inputting, to the second data buffer, the data of said plurality of pages after correcting the erroneous data;
swapping the data of the second data buffer with the data of the first data buffer; and
writing the data of the first data buffer in an area different from an area of the memory cell array from which the data is read, wherein error correction calculation and correction operation for a page next to a given page subjected to read or write is performed during read or write of the given page. - View Dependent Claims (14, 15)
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16. A data copy method for a memory system in which a plurality of pages are transferred and copied from a copy source block to a copy destination block in a flash memory having a memory cell array, a first page buffer, a second page buffer, and an error correction circuit, comprising:
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storing first page data of the copy source block in the first page buffer;
storing second page data of the copy source block in the second page buffer;
starting a program procedure from the first page buffer and the second page buffer for the copy destination block of the memory cell array in order to program the first page data of the copy source block; and
starting an ECC verify procedure in order to verify the second page data of the copy source block in the second page buffer, wherein the program procedure and the ECC verify procedure are simultaneously executed. - View Dependent Claims (17, 18, 19)
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Specification