Memory system which copies successive pages, and data copy method therefor

• US 20060050314A1
• Filed: 09/01/2005
• Published: 03/09/2006
• Est. Priority Date: 09/03/2004
• Status: Active Grant

• Current Assignee: Kioxia Corporation, Solid State System Co., Ltd.
• Original Assignee: Solid State System Co., Ltd., Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shiga, Hitoshi, Wang, Chih-Hung, Chen, Chih-Chung, Hung, Sheng-Lin
• Granted Patent: US 7,372,744 B2
• Time in Patent Office: Days
• US Class Current: 358/1.160
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Claims

1. A memory system comprising:

a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;

a first data buffer which holds, in read, data read from the memory cell array via a bit line switch and in write, data to be written in the memory cell array via the bit line switch;

a second data buffer which is configured to swap data with the first data buffer, copies data to the first data buffer, and receives a copy of data from the first data buffer;

a bus switch which is interposed between the second data buffer and a bus, selects part of data held by the second data buffer, and transfers the part of data to the bus;

an error correction circuit which is connected to the bus and performs error correction calculation of data read from the memory cell array; and

a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads, page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls to perform write in the second block in an erase state in the memory cell array.

2. A system according to claim 1, wherein the first data buffer has a functional unit serving as a sense amplifier and a functional unit serving as a data cache, and the functional unit serving as the data cache holds sense data in read and write data in write.

3. A system according to claim 1, wherein the first data buffer comprises a register which statically holds data, a temporary register which dynamically holds data, and a switch circuit which controls data transfer between the register and the temporary register, between the register and the second data buffer, and between the temporary register and the second data buffer.

4. A system according to claim 1, wherein the first data buffer exchanges data for each page with the second data buffer.

5. A system according to claim 1, wherein the first data buffer is divided into a plurality of areas, and data is reset for each sector.

6. A system according to claim 5, wherein reset of each sector is simultaneously executed for arbitrary sectors.

7. A system according to claim 5, further comprising a third data buffer which is interposed between the second data buffer and the bus switch and holds data for complementing data of a reset sector via the bus.

8. A system according to claim 1, wherein the control circuit controls verify operation of whether write is normally done upon read after write in the memory cell array, and when a verify result represents fail, outputs a status representing that page copy operation fails and a fail address.

9. A system according to claim 2, wherein the control circuit comprises a page buffer control circuit which controls the bit line switch, the first data buffer, and the second data buffer, and controls data transfer between the memory cell array, the first data buffer, and the second data buffer and sense operation of the functional unit serving as the sense amplifier in the first data buffer, and an internal controller which performs control for page copy, read, write, and erase.

10. A memory system comprising:

a memory cell array in which electrically rewritable nonvolatile memory cells are arrayed;

a first data buffer and a second data buffer which hold, in read, data read from the memory cell array and in write, data to be written in the memory cell array;

a bit line switch which connects one of the first data buffer and the second data buffer to the memory cell array;

a bus switch which connects, to a bus, one of the first data buffer and the second data buffer that is not connected to the memory cell array;

an error correction circuit which is connected to the bus and performs error correction calculation of data read from the memory cell array; and

a control circuit which controls the bit line switch, the first data buffer, and the second data buffer, sequentially reads, page by page, at least one page from an mth (m is a positive integer) page to an nth (n is an integer greater than m) page of a first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first data buffer, the second data buffer, and the bit line switch, and controls to perform write in the second block in an erase state in the memory cell array.

11. A system according to claim 10, wherein the bit line switch comprises a first bit line switch which is interposed between a bit line in the memory cell array and the first data buffer and controls data transfer between the memory cell array and the first data buffer under control of the control circuit, and a second bit line switch which is interposed between the bit line in the memory cell array and the second data buffer and controls data transfer between the memory cell array and the second data buffer under control of the control circuit.

12. A system according to claim 11, wherein the first data buffer is connected to the bit line of the memory cell array via the first bit line switch, and the second data buffer is connected to the bit line of the memory cell array via the second bit line switch.

13. A page copy method for a memory system, comprising:

reading, page by page, data of a plurality of pages at successive page addresses from a memory cell array to a first data buffer;

swapping data read to the first data buffer with data of a second data buffer;

executing error correction calculation for the readout data of said plurality of pages;

correcting erroneous data detected by the error correction calculation;

inputting, to the second data buffer, the data of said plurality of pages after correcting the erroneous data;

swapping the data of the second data buffer with the data of the first data buffer; and

writing the data of the first data buffer in an area different from an area of the memory cell array from which the data is read,

wherein error correction calculation and correction operation for a page next to a given page subjected to read or write is performed during read or write of the given page.

14. A method according to claim 13, wherein when page copy of copying an mth page (m is a positive integer) to an nth page (n is an integer greater than m) of a first block in the memory cell array to a second block normally ends up to a pth (p is an integer greater than m but less than n) page and fails at a qth (q is an integer greater than p) page, the mth page to the pth page are copied from the second block to a third block, and the qth page to the nth page are copied from the first block to the third block.

15. A method according to claim 14, wherein no error correction calculation and no error correction are performed when the mth page to the pth page are copied from the second block to the third block.

16. A data copy method for a memory system in which a plurality of pages are transferred and copied from a copy source block to a copy destination block in a flash memory having a memory cell array, a first page buffer, a second page buffer, and an error correction circuit, comprising:

storing first page data of the copy source block in the first page buffer;

storing second page data of the copy source block in the second page buffer;

starting a program procedure from the first page buffer and the second page buffer for the copy destination block of the memory cell array in order to program the first page data of the copy source block; and

starting an ECC verify procedure in order to verify the second page data of the copy source block in the second page buffer,

wherein the program procedure and the ECC verify procedure are simultaneously executed.

17. A method according to claim 16, which further comprises starting an address calculation procedure for a third page of the copy source block, and in which the address calculation procedure and the program procedure are simultaneously executed.

18. A method according to claim 16, which further comprises starting an address calculation procedure for a third page of the copy source block, and in which the address calculation procedure and the ECC verify procedure are simultaneously executed.

19. A method according to claim 16, further comprising swapping the first page data of the copy source block in the first page buffer and the second page data of the copy source block in the second page buffer.