Nonvolatile semiconductor memory device

• US 20060050559A1
• Filed: 09/06/2005
• Published: 03/09/2006
• Est. Priority Date: 09/07/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iizuka, Yoshio, Sakui, Koji
• Granted Patent: US 7,242,613 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The nonvolatile semiconductor memory device of this invention has a trench region in a semiconductor substrate and has a NAND type memory cell unit in three dimensions in both sides of a side wall of one trench region, respectively. And these NAND memory cell units are connected to one bit line. In each NAND type memory cell unit, a plurality of the memory cell transistors and the selective gate transistors are connected in series. These pluralities of the memory cell transistors and the selective gate transistors are provided in the same trench region. Moreover, in the nonvolatile semiconductor memory device of this invention, an insulating layer containing a lamination structure of a silicon oxide film, a silicon nitride film and a silicon oxide film, or silicon, or metal or other nano crystals of conductivity substance is used for an electric charge accumulation layer of the memory cell transistor instead of a conventional floating gate.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array having a first NAND type memory cell unit connecting a plurality of 1st memory cell transistor in-series which a 1st electric charge accumulation layer and control gate are laminated, and a second NAND type memory cell unit connecting in-series a plurality of second memory cell transistor which 2nd electric charge accumulation layer and said control gate are laminated are arranged in the shape of an array, and

wherein said 1st memory cell transistor and said 2nd memory cell transistor are formed to face each other along with both-sides of wall of a trench formed on a semiconductor substrate respectively, sharing said one control gate formed by extending in a depth direction of said trench;

wherein said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistor and said 2nd electric charge accumulation layer of said 2nd memory cell transistor, and electrically connects with a word line extending continuously; and

wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are respectively formed by laminating silicon oxide film, a silicon nitride film and silicon oxide film in order, and said control gate is made of poly silicon doped with impurities or metal.

2. A nonvolatile semiconductor memory device according to claim 1, wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are made of the same continuous layer.

3. A nonvolatile semiconductor memory device according to claim 1, wherein said 1st NAND type memory cell unit and said 2nd NAND type memory cell unit are connected to the same bit line.

4. A nonvolatile semiconductor memory device comprising:

a memory cell array having 1st NAND type memory cell unit and 2nd NAND type memory cell unit,

the 1st memory cell unit having 1st NAND type memory cell array connecting in-series a plurality of 1st memory cell transistor which the 1st electric charge accumulation layer and control gate are laminated, 1st switch part at source line side connecting between said 1st NAND type memory cell array and a common source line, and the 1st switch part at bit line side connected between the 1st NAND type memory cell array and the bit line,

the 2nd memory cell unit having 2nd NAND type memory cell array connecting in-series a plurality of 2nd memory cell transistor which the 2nd electric charge accumulation layer and the control gate are laminated, 2nd switch part at source line side connecting between said 2nd NAND type memory cell array and the common source line, and the 2nd switch part at bit line side connected between the 2nd NAND type memory cell array and the bit line,

wherein said 1st memory cell transistor and said 2nd memory cell transistor are formed respectively to face each other along with both-sides of wall of a trench formed on a semiconductor substrate, sharing said one control gate formed by extending in a depth direction of said trench,

wherein said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistor and said 2nd electric charge accumulation layer of said 2nd memory cell transistor, and electrically connects with a word line extending continuously, and

wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are respectively formed by laminating silicon oxide film, a silicon nitride film and silicon oxide film in order, and said control gate is made of poly silicon doped with impurities or metal.

5. A nonvolatile semiconductor memory device according to claim 4, wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are made of the same continuous layer.

6. A nonvolatile semiconductor memory device comprising:

a memory cell array having a first NAND type memory cell unit connecting a plurality of 1st memory cell transistor in-series which a 1st electric charge accumulation layer and control gate are laminated and a second NAND type memory cell unit connecting in-series a plurality of second memory cell transistor which 2nd electric charge accumulation layer and said control gate are laminated, are arranged in the shape of an array, and

wherein said 1st memory cell transistor and said 2nd memory cell transistor are formed respectively to face each other along with both-sides of wall of a trench formed on a semiconductor substrate, sharing said one control gate formed by extending in a depth direction of said trench, and

said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistor and said 2nd electric charge accumulation layer of said 2nd memory cell transistor, electrically connecting with a word line extending continuously, and

wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer respectively comprises an insulating layer including silicon, metal or conductive nano crystal and said control gate is made of poly silicon doped with impurities or metal.

7. A nonvolatile semiconductor memory device according to claim 6, wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer consists of the same continuous layer.

8. A nonvolatile semiconductor memory device according to claim 6, wherein said 1st NAND type memory cell unit and said 2nd NAND type memory cell unit are connected to the same bit line.

9. A nonvolatile semiconductor memory device comprising:

a memory cell array having 1st NAND type memory cell unit and 2nd NAND type memory cell unit,

the 1st memory cell unit having 1st NAND type memory cell array connecting in-series a plurality of 1st memory cell transistor which the 1st electric charge accumulation layer and control gate are laminated, 1st switch part at source line side connecting between said 1st NAND type memory cell array and a common source line, and the 1st switch part at bit line side connected between the 1st NAND type memory cell array and the bit line,

the 2nd memory cell unit having 2nd NAND type memory cell array connecting in-series a plurality of 2nd memory cell transistor which the 2nd electric charge accumulation layer and the control gate are laminated, 2nd switch part at source line side connecting between said 2nd NAND type memory cell array and the common source line, and the 2nd switch part at bit line side connected between the 2nd NAND type memory cell array and the bit line,

wherein the 1st memory cell transistor and said 2nd memory cell transistor are formed respectively to face each other along with both-sides of wall of a trench formed on a semiconductor substrate, sharing said one control gate formed by extending in a depth direction of said trench, and

said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistor and said 2nd electric charge accumulation layer of said 2nd memory cell transistor, electrically connecting with a word line extending continuously, and

wherein the 1st electric charge accumulation layer and said 2nd electric charge accumulation layer respectively comprise an insulating layer including silicon, metal or conductive nano-crystal, and said control gate is made of poly silicon doped with impurities or metal.

10. A nonvolatile semiconductor memory device according to claim 9, wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer consist of the same continuous layer.