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Nonvolatile semiconductor memory device

  • US 20060050559A1
  • Filed: 09/06/2005
  • Published: 03/09/2006
  • Est. Priority Date: 09/07/2004
  • Status: Active Grant
First Claim
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1. A nonvolatile semiconductor memory device comprising:

  • a memory cell array having a first NAND type memory cell unit connecting a plurality of 1st memory cell transistor in-series which a 1st electric charge accumulation layer and control gate are laminated, and a second NAND type memory cell unit connecting in-series a plurality of second memory cell transistor which 2nd electric charge accumulation layer and said control gate are laminated are arranged in the shape of an array, and wherein said 1st memory cell transistor and said 2nd memory cell transistor are formed to face each other along with both-sides of wall of a trench formed on a semiconductor substrate respectively, sharing said one control gate formed by extending in a depth direction of said trench;

    wherein said control gate is formed between said 1st electric charge accumulation layer of said 1st memory cell transistor and said 2nd electric charge accumulation layer of said 2nd memory cell transistor, and electrically connects with a word line extending continuously; and

    wherein said 1st electric charge accumulation layer and said 2nd electric charge accumulation layer are respectively formed by laminating silicon oxide film, a silicon nitride film and silicon oxide film in order, and said control gate is made of poly silicon doped with impurities or metal.

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