Using transfer bits during data transfer from non-volatile to volatile memories

• US 20060050567A1
• Filed: 11/01/2005
• Published: 03/09/2006
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Shimanek, Schuyler E., Darling, Roy D.
• Granted Patent: US 7,127,552 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

Structures and methods for transferring data from non-volatile to volatile memories. An extra bit, called a “transfer bit”, is included in each data word. The transfer bit is set to the programmed value, and is monitored by a control circuit during the memory transfer. If the supply voltage is sufficient for correct programming, the transfer bit is read as “programmed”, and the data transfer continues. If the supply voltage is below the minimum supply voltage for proper programming, the transfer bit is read as “erased”, and the data transfer is reinitiated. In one embodiment, a second transfer bit set to the “erased” value is included in each word.

Claims

1. An initialization circuit, comprising:

a non-volatile memory including a plurality of words, each word including a first transfer bit having a first stored value that is one of a “

programmed”

value and an “

erased value”

, the non-volatile memory having an input port, an output port, and a control input port;

a sensing array having an input port coupled to the output port of the non-volatile memory and an output port, the output port including a first terminal on which a sensed first transfer bit is placed;

a volatile memory having an input port coupled to the output port of the sensing array and a control input port; and

a control circuit coupled to the first terminal of the sensing array and the control input ports of the non-volatile and volatile memories.

2. The initialization circuit of claim 1, wherein the first transfer bit is in the same location of each word.

3. The initialization circuit of claim 1, wherein:

each word further includes a second transfer bit having a second stored value, the second stored value being different from the first stored value;

the sensing array output port further includes a second terminal on which a sensed second transfer bit is placed; and

the control circuit is further coupled to the second terminal of the sensing array.

4. The initialization circuit of claim 1, wherein the control circuit comprises a latch coupled to the first terminal of the sensing array.

5. The initialization circuit of claim 1, wherein the initialization circuit comprises a portion of a programmable logic device.

6. The initialization circuit of claim 5, wherein the plurality of words comprises configuration data for the programmable logic device.

7. The initialization circuit of claim 5, wherein the programmable logic device is a CPLD.