Memory circuit with supply voltage flexibility and supply voltage adapted performance
First Claim
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1. A memory circuit comprising:
- a plurality of memory cells organized in rows and columns;
memory access circuitry controlled by at least one control signal; and
control circuitry for generating the at least one control signal comprising;
delay circuitry which delays a switching of the at least one control signal with the respective delay time being adjustable in view of the applied supply voltage.
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Abstract
The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.
23 Citations
27 Claims
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1. A memory circuit comprising:
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a plurality of memory cells organized in rows and columns;
memory access circuitry controlled by at least one control signal; and
control circuitry for generating the at least one control signal comprising;
delay circuitry which delays a switching of the at least one control signal with the respective delay time being adjustable in view of the applied supply voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for operating a memory device, the method comprising:
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determining whether a power supply voltage of the memory device is a first voltage or a second voltage;
if the power supply voltage of the memory device is the first voltage, placing a driver in a first mode, in which a first drive strength of the driver is used to generate a control signal delayed by a first delay; and
if the power supply voltage of the memory device is the second voltage, placing the driver in a second mode in which a second drive strength of the driver is used to generate the control signal delayed by a second delay. - View Dependent Claims (8, 9, 10, 11)
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12. A memory device, comprising:
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a driver having a first mode with a corresponding first drive strength and a second mode with a corresponding second drive strength; and
control circuitry configured to;
determine whether a power supply voltage of the memory device is a first voltage or a second voltage;
if the power supply voltage of the memory device is the first voltage, place the driver in the first mode in which the first drive strength of the driver is used to generate a control signal delayed by a first delay; and
if the power supply voltage of the memory device is the second voltage, place the driver in the second mode in which the second drive strength of the driver is used to generate the control signal delayed by a second delay. - View Dependent Claims (13, 14, 15, 16)
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17. A memory device comprising:
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means for driving having a first mode with a corresponding first drive strength and a second mode with a corresponding second drive strength;
means for controlling configured to;
determine whether a power supply voltage of the memory device is a first voltage or a second voltage;
if the power supply voltage of the memory device is the first voltage, place the means for driving in the first mode in which the first drive strength of the means for driving is used to generate a control signal delayed by a first delay; and
if the power supply voltage of the memory device is the second voltage, place the means for driving in the second mode in which the second drive strength of the means for driving is used to generate the control signal delayed by a second delay. - View Dependent Claims (18, 19, 20, 21)
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22. A memory device comprising:
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a driver having a first mode and a second mode, wherein the driver comprises;
first transistors for providing a first drive strength when the driver is in the first mode; and
second transistors for providing a second drive strength when the driver is in the second mode;
control circuitry configured to;
determine whether the memory device is in a high power mode or a low power mode;
if the memory device is in the high power mode, place the driver in the first mode in which the first drive strength is used to generate a control signal delayed by a first delay; and
if the memory device is in the high power mode, place a driver in the first mode in which the second drive strength is used to generate a control signal delayed by a first delay. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification