Row decoder for NAND memories
First Claim
1. A row decoder for an electrically programmable NAND memory including an array of a plurality of memory cells arranged in a plurality of rows, said memory cells being grouped into a plurality of memory blocks each one including a plurality of strings of memory cells, and each string including at least one access element for coupling the string to a respective bit line, the access elements of the strings of a respective memory block being controlled by a respective select line, the row decoder including:
- a global select line selectively couplable to the select line corresponding to an addressed memory block;
switching means for each memory block for selectively coupling the global select line to the select line, the switching means having a respective control node; and
precharging means for precharging to a select voltage the control nodes, the precharging means being activatable in a testing operation for precharging all the control nodes to the select voltage adapted to cause the coupling of the global select line to the select lines, wherein the row decoder further includes;
first means for keeping at least the control node of the addressed memory block charged at said select voltage;
second means for decoupling all the select lines from the global select line; and
third means for providing an access voltage to the select line corresponding to the addressed memory block for enabling the respective access elements and for providing an access inhibition voltage to the select lines corresponding to the non-addressed memory block, the first, second and third means being activatable in the testing operation.
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Accused Products
Abstract
A row decoder for an electrically programmable NAND memory further includes a first means for keeping at least a control node of an addressed memory block charged at a select voltage. A second means decouples all select lines from a global select line. A third means provides an access voltage to the select line corresponding to an addressed memory block for enabling respective access elements and for providing an access inhibition voltage to the select lines corresponding to a non-addressed memory block. The first, second and third means are activatable in a testing operation.
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Citations
20 Claims
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1. A row decoder for an electrically programmable NAND memory including an array of a plurality of memory cells arranged in a plurality of rows, said memory cells being grouped into a plurality of memory blocks each one including a plurality of strings of memory cells, and each string including at least one access element for coupling the string to a respective bit line, the access elements of the strings of a respective memory block being controlled by a respective select line, the row decoder including:
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a global select line selectively couplable to the select line corresponding to an addressed memory block;
switching means for each memory block for selectively coupling the global select line to the select line, the switching means having a respective control node; and
precharging means for precharging to a select voltage the control nodes, the precharging means being activatable in a testing operation for precharging all the control nodes to the select voltage adapted to cause the coupling of the global select line to the select lines, wherein the row decoder further includes;
first means for keeping at least the control node of the addressed memory block charged at said select voltage;
second means for decoupling all the select lines from the global select line; and
third means for providing an access voltage to the select line corresponding to the addressed memory block for enabling the respective access elements and for providing an access inhibition voltage to the select lines corresponding to the non-addressed memory block, the first, second and third means being activatable in the testing operation. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In an electrically programmable NAND memory including an array of a plurality of memory cells arranged in a plurality of rows, said memory cells being grouped into a plurality of memory blocks each one including a plurality of strings of memory cells, and each string including at least one access element for coupling the string to a respective bit line, the access elements of the strings of a respective memory block being controlled by a respective select line, a global select line selectively couplable to the select line corresponding to an addressed memory block, switching means for each memory block for selectively coupling the global select line to the select line, the switching means having a respective control node, and means for precharging to a select voltage the control nodes,
a method of testing a memory cell including precharging all the control nodes to the select voltage adapted to cause the coupling of the global select line to the select line, wherein the method further includes: -
keeping at least the control node of the addressed memory block charged at said selection voltage;
decoupling all the select lines from the global select line;
providing an access voltage to the select line corresponding to the addressed memory block for enabling the respective access elements; and
providing an access inhibition voltage to the select lines corresponding to the non-addressed memory block. - View Dependent Claims (8, 9, 10, 11)
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12. A row decoder for an electrically programmable NAND memory including an array of memory cells arranged rows and columns, each memory cell in a given column being associated with a corresponding bit line and the memory cells being grouped into a plurality of memory blocks, each block including a plurality of strings of memory cells with each string including a plurality of memory cells associated with the corresponding bit line and at least one access element for coupling the string to the bit line, each access element of each string being adapted to receive a respective select signal from the row decoder, the row decoder comprising:
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a plurality of first pass switching circuits, each first pass switching circuit being associated with a corresponding memory block and each pass switching circuit having a control node adapted to receive a block enable signal, an output node coupled to the access elements of the strings in the block, and having an input node;
a plurality of second pass switching circuits, each second pass switching circuit being associated with a corresponding memory block and having a control node adapted to receive an enable signal, an output node coupled to input node of the corresponding first pass switching circuit, and having an input node adapted to receive a global selection signal;
a plurality of third pass switching circuits, each third pass switching circuit being associated with a corresponding memory block and having a control node adapted to receive a test mode enable signal, an output node coupled to input node of the corresponding first pass switching circuit, and having an input node adapted to receive a test activation signal; and
a plurality of precharge control circuits, each precharge control circuit being associated with a corresponding memory block and adapted to receive a corresponding block selection signal and to receive a precharge signal and a discharge signal, and each precharge control circuit coupled to the control node of the corresponding first pass switching circuit to apply the block enable signal, coupled to the input node of the corresponding third pass switching circuit to apply the test activation signal. - View Dependent Claims (13, 14, 15, 16)
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17. An electronic device, comprising:
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an electronic subsystem including an electrically programmable NAND memory including an array of memory cells arranged rows and columns, each memory cell in a given column being associated with a corresponding bit line and the memory cells being grouped into a plurality of memory blocks, each block including a plurality of strings of memory cells with each string including a plurality of memory cells associated with the corresponding bit line and at least one access element for coupling the string to the bit line, each access element of each string being adapted to receive a respective select signal from the row decoder;
a row decoder including, a plurality of first pass switching circuits, each first pass switching circuit being associated with a corresponding memory block and each pass switching circuit having a control node adapted to receive a block enable signal, an output node coupled to the access elements of the strings in the block, and having an input node;
a plurality of second pass switching circuits, each second pass switching circuit being associated with a corresponding memory block and having a control node adapted to receive an enable signal, an output node coupled to input node of the corresponding first pass switching circuit, and having an input node adapted to receive a global selection signal;
a plurality of third pass switching circuits, each third pass switching circuit being associated with a corresponding memory block and having a control node adapted to receive a test mode enable signal, an output node coupled to input node of the corresponding first pass switching circuit, and having an input node adapted to receive a test activation signal; and
a plurality of precharge control circuits, each precharge control circuit being associated with a corresponding memory block and adapted to receive a corresponding block selection signal and to receive a precharge signal and a discharge signal, and each precharge control circuit coupled to the control node of the corresponding first pass switching circuit to apply the block enable signal, coupled to the input node of the corresponding third pass switching circuit to apply the test activation signal. - View Dependent Claims (18)
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19. A method of testing memory cells in an electrically programmable NAND memory including an array of memory cells arranged rows and columns, each memory cell in a given column being associated with a corresponding bit line and the memory cells being grouped into a plurality of memory blocks, each block including a plurality of strings of memory cells with each string including a plurality of memory cells associated with the corresponding bit line and at least one access element for coupling the string to the bit line, each access element of each string being adapted to receive a respective select signal on an input node, and including a pass circuit coupled to the input node of each access element and having control nodes, the method comprising:
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precharging the control nodes of all pass circuits to a select voltage adapted to cause the coupling of a global select signal to the input node of each access element;
driving at least the control node of the pass circuit associated with an addressed memory block at the select voltage;
isolating all the select lines from receiving the global select signal;
providing an access voltage through the pass circuit corresponding to the addressed memory block to the select line for enabling the respective access elements in that block; and
providing an access inhibition voltage through the pass circuits for all non-addressed memory blocks to the select lines for these non-addressed memory blocks. - View Dependent Claims (20)
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Specification