Wireless state machine and multiplexing method for concurrent ad-hoc and infrastructure mode service in wireless networking

• US 20060050729A1
• Filed: 09/08/2004
• Published: 03/09/2006
• Est. Priority Date: 09/08/2004
• Status: Active Grant

• Current Assignee: Canon USA, Inc. (Canon Inc.)
• Original Assignee: Canon USA, Inc. (Canon Inc.)
• Inventors: Chen, Paul, Wilson, Richard A. Jr.
• Granted Patent: US 7,680,087 B2
• Time in Patent Office: Days
• US Class Current: 370/450
• CPC Class Codes: H04W 36/00 Hand-off or reselection arrangements
• CPC Class Codes: H04W 40/02 Communication route or path selection, e.g. power-based or shortest path routing
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks
• CPC Class Codes: H04W 88/00 Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices

Abstract

The present invention relates to a state machine which has a dual process which receives and concurrently processes ad-hoc and infrastructure processes. The dual process state concurrently executes both processes by either over-clocking a media access control core, or by routing the processes to multiple media access control cores for processing. The state machine contains an ad-hoc process state which accepts either an ad-hoc or an infrastructure signal, and either processes the signal if the received signal is an ad-hoc signal, or transfers control to an infrastructure process state for processing if the received signal is an infrastructure signal. The state machine also contains an infrastructure process state which accepts either an ad-hoc or an infrastructure signal, and either processes the signal if the received signal is an infrastructure signal, or transfers control to an ad-hoc process state for processing if the received signal is an ad-hoc signal.

Claims

1. A state machine comprising:

a dual process state;

a first process state configured to receive a first signal and a second signal, to execute a first process upon receipt of the first signal, and to transition to the dual process state for processing upon receipt of the second signal; and

a second process state configured to receive the first signal and the second signal, to execute a second process upon receipt of the second signal, and to transition to the dual process state for processing upon receipt of the first signal,

wherein the dual process state is configured to execute the first process and the second process, to transition to the first process state after executing the second process, and to transition to the second process state after executing the first process.

2. The state machine according to claim 1, further comprising:

a first wait state;

a first timeout period;

a second wait state; and

a second timeout period,

wherein the first wait state transitions to the second wait state if the first signal has either not been sent or has not been received within the first timeout period, and

wherein the second wait state transitions to the first wait state if the second signal has either not been sent or has not been received within the second timeout period.

3. The state machine according to claim 2,

wherein the first wait state transitions to the first process state for processing if the first signal has either been sent or received within the first timeout period,

wherein the first process state transitions to the first wait state after executing the first process,

wherein the second wait state transitions to the second process state for processing if the second signal has either been sent or received within the second timeout period, and

wherein the second process state transitions to the second wait state after executing the second process.

4. The state machine according to claim 2, further comprising:

a counting mechanism configured to count the occurrences of the first signal and the second signal,

wherein the first timeout period is increased and the second timeout period is decreased if the count of the first signal is greater than the count of the second signal, and

wherein the second timeout period is increased and the first timeout period is decreased if the count of the second signal is greater than the count of the first signal.

5. The state machine according to claim 2,

wherein a user increases or decreases the first timeout period and the second timeout period.

6. The state machine according to claim 1,

wherein the first process is an ad-hoc process, the first process state is an ad-hoc process state, and the first signal is an ad-hoc request-to-send signal or an ad-hoc clear-to-send signal, and

wherein the second process is an infrastructure process, the second process state is an infrastructure process state, and the second signal is an infrastructure request-to-send signal or an infrastructure clear-to-send signal.

7. The state machine according to claim 2,

wherein the first wait state is an ad-hoc wait state and the second wait state is an infrastructure wait state,

wherein the first timeout period is a first predetermined period to wait for the ad-hoc clear-to-send or the ad-hoc request-to-send signal, and

wherein the second timeout period is a second predetermined period to wait for the infrastructure clear-to-send signal or the infrastructure request-to-send signal.

8. The state machine according to claim 1,

wherein the state machine operates within a wireless device.

9. An apparatus comprising:

a first processing core configured to execute a first process;

a second processing core configured to execute a second process;

a radio control port configured to detect and process a first signal and a second signal;

an auxiliary control system, coupled to the radio control port, the first processing core, and the second processing core, which activities and deactivates the first processing core for executing the first process and the second processing core for executing the second process.

10. An apparatus according to claim 9, wherein the auxiliary control system comprises:

a first timeout period and a second timeout period,

wherein the first processing core is activated during the first timeout period and deactivated after the first timeout period has expired, and wherein the second processing core is activated during the second timeout period and deactivated after the second timeout period has expired.

11. An apparatus according to claim 9,

wherein the radio control port detects the first signal, requests the auxiliary control system to activate the first processing core, and the first processing core executes the first process, and

wherein the radio control port detects the second signal, requests the auxiliary control system to activate the second processing core, and the second processing core executes the second process.

12. An apparatus according to claim 9,

wherein the auxiliary control system deactivates the first processing core upon completion of execution of the first process and deactivates the second processing core upon completion of execution of the second process.

13. An apparatus according to claim 9, further comprising:

a radio data interface coupled to the radio control port;

a first serial control apparatus coupled to the radio control port and the first processing core; and

a second serial control apparatus coupled to the radio control port and the second processing core,

wherein the radio data interface processes a plurality of radio signals into a plurality of data,

wherein the first serial control apparatus processes the data into a plurality of serial data and sends the serial data to the first processing core, and

wherein the second serial control apparatus processes the data into a plurality of serial data and sends the serial data to the second processing core.

14. An apparatus according to claim 9,

wherein the radio control port detects the first signal, requests the auxiliary control system to activate both the first processing core and the second processing core, and executes the first process via the first processing core and the second processing core,

and wherein the radio control port detects the second signal, requests the auxiliary control system to activate both the first processing core and the second processing core, and executes the first process via the first processing core and the second processing core.

15. An apparatus according to claim 10,

wherein the first timeout period is a first predetermined period to wait for the ad-hoc clear-to-send or the ad-hoc request-to-send signal, and

wherein the second timeout period is a second predetermined period to wait for the infrastructure clear-to-send signal or the infrastructure request-to-send signal.

16. An apparatus according to claim 10, further comprising:

a counting mechanism configured to count the occurrences of the first signal and the second signal,

wherein the first timeout period is increased and the second timeout period is decreased if the count of the first signal is greater than the count of the second signal,

wherein the second timeout period is increased and the first timeout period is decreased if the count of the second signal is greater than the count of the first signal.

17. An apparatus according to claim 10,

wherein a user increases or decreases the first timeout period and the second timeout period.

18. An apparatus according to claim 9,

wherein the first process is an ad-hoc process,

the second process is an infrastructure process,

the first signal is an ad-hoc request-to-send or an ad-hoc clear-to-send signal, and

the second signal is an infrastructure request-to-send or an infrastructure clear-to-send signal.

19. An apparatus according to claim 9,

wherein the first process is an infrastructure process,

the second process is an ad-hoc process,

the first signal is an infrastructure request-to-send or an infrastructure clear-to-send signal, and

the second signal is an ad-hoc request-to-send or an ad-hoc clear-to-send signal.

20. An apparatus according to claim 9, wherein the first processing core is a media access control core and the second processing core is a media access control core.

21. An apparatus comprising:

a first processing core configured to execute either a first process or a second process;

a second processing core configured to execute either the first process or the second process;

a radio control port configured to detect and process a first signal and a second signal;

an auxiliary control system, coupled to the radio control port, the first processing core, and the second processing core, wherein the auxiliary control system activities and deactivates the first processing core for executing either the first process or the second process and activates and deactivates the second processing core for executing either the first process or the second process.

22. An apparatus according to claim 21,

wherein the auxiliary control system toggles the first processing core to execute the first process or the second process, and toggles the second processing core to execute the first process or second process.

23. An apparatus according to claim 21, wherein the auxiliary control system comprises:

a first timeout period and a second timeout period;

wherein the first processing core is toggled to execute the first process during the first timeout period, and

wherein the first processing core is toggled to execute the second process during the second timeout period.

24. An apparatus according to claim 23,

the radio control port requests the auxiliary control system to toggle the first processing core to execute the first process.

25. An apparatus according to claim 23,

the radio control port requests the auxiliary control system to toggle the first processing core to execute the second process.

26. An apparatus according to claim 21, wherein the radio control port detects the second signal while the first processing core is executing the first process, and

requests the auxiliary control system to activate the second processing core and to toggle the second processing core to execute the second process.

27. An apparatus according to claim 21, wherein the auxiliary control system deactivates the second processing core upon the second processing core'"'"'s completing execution of either the first process or the second process.

28. An apparatus according to claim 21, further comprising:

a first serial control apparatus coupled to the radio control port and the first processing core;

a second serial control apparatus coupled to the radio control port and the second processing core;

a radio data interface coupled to the radio control port,

wherein the radio data interface processes a plurality of radio signals into a plurality of data,

wherein the first serial control apparatus processes the data into a plurality of serial data, and sends the serial data to the first processing core, and

wherein the second serial control apparatus processes the data into a plurality of serial data, and sends the serial data to the second processing core.

29. An apparatus according to claim 21,

wherein the radio control port detects the first signal, requests the auxiliary control system to activate both the first processing core and the second processing core, and executes the first process via the first processing core and the second processing core,

and wherein the radio control port detects the second signal, requests the auxiliary control system to activate both the first processing core and the second processing core, and executes the first process via the first processing core and the second processing core.

30. An apparatus according to claim 23, further comprising:

a counting mechanism configured to count the occurrences of the first signal and the second signal,

wherein the first timeout period is increased and the second timeout period is decreased if the count of the first signal is greater than the count of the second signal,

wherein the second timeout period is increased and the first timeout period is decreased if the count of the second signal is greater than the count of the first signal.

31. An apparatus according to claim 23,

wherein a user increases or decreases the first timeout period and the second timeout period.

32. An apparatus according to claim 21,

wherein the first process is either an ad-hoc process or an infrastructure process, whichever process arrives first at the radio data interface,

wherein the second process is either an ad-hoc process or an infrastructure process, whichever process arrives second at the radio data interface,

wherein the first signal is either an ad-hoc request-to-send signal, an ad-hoc clear-to-send signal, an infrastructure request-to-send signal, or an infrastructure clear-to-send signal, whichever signal arrives first at the radio data interface, and

wherein the second signal is either an ad-hoc request-to-send signal, an ad-hoc clear-to-send signal, an infrastructure request-to-send signal, or an infrastructure clear-to-send signal, whichever signal arrives second at the radio data interface.

33. An apparatus according to claim 21, wherein the first processing core is a first media access control core and the second processing core is a second media access control core.

34. An apparatus comprising:

a radio control port configured to detect and process a first signal and a second signal;

a processing core, coupled to the radio control port, configured to execute either a first process or a second process;

a mode control apparatus, coupled to the processing core and the radio control port, configured to toggle the processing core to execute either the first process or the second process; and

a clocking apparatus, coupled to the processing core, the mode control apparatus, and the radio control port, configured to set a clock for the apparatus at a normal clocked rate and an over-clocked rate.

35. An apparatus according to claim 34, further comprising:

a serial control apparatus, coupled to the radio control port, the processing core, and the clocking apparatus;

a radio data interface, coupled to the radio control port, configured to process a plurality of radio signals into a plurality of data;

wherein the serial control apparatus processes the data into a plurality of serial data, and

sends the serial data to the processing core.

36. An apparatus according to claim 34,

wherein the clocking apparatus is coupled to the radio interface and the serial control apparatus,

wherein the clocking apparatus sets the clock for the radio interface, the radio control port, and the serial control apparatus at the over-clocked rate, and

wherein the over-clocked rate is a multiple higher than the normal clocked rate.

37. An apparatus according to claim 34,

wherein, during a first timeout period, the radio control port detects the first signal, and requests the mode control apparatus to toggle the processing core to execute the first process, and

wherein, during a second timeout period, the radio control port detects the second signal, and requests the mode control apparatus to toggle the processing core to execute the second process.

38. An apparatus according to claim 37, further comprising:

a counting mechanism configured to count the occurrences of the first signal and the second signal,

wherein the first timeout period is increased and the second timeout period is decreased if the count of the first signal is greater than the count of the second signal,

wherein the second timeout period is increased and the first timeout period is decreased if the count of the second signal is greater than the count of the first signal.

39. An apparatus according to claim 37,

wherein a user increases or decreases the first timeout period and the second timeout period.

40. An apparatus according to claim 34,

wherein the radio control port detects the second signal while the processing core executes the first process,

requests the clocking apparatus to set the processing core at the over-clocked rate, and

requests the mode control apparatus to toggle the processing core to alternate between executing the first process and the second process at the over-clocked rate in response to detecting the second signal while the processing core executes the first process.

41. An apparatus according to claim 34,

wherein the processing core completes executing either the first process or the second process,

the clocking apparatus sets the processing core at the normal clocked-rate,

and the mode control apparatus controls the processing core to execute either the first process or the second process.

42. An apparatus according to claim 34,

wherein the first process is either an ad-hoc process or an infrastructure process, whichever arrives first at the radio data interface,

the second process is either an ad-hoc process or an infrastructure process, whichever arrives second at the radio data interface,

the first signal is either an ad-hoc request-to-send signal, an ad-hoc clear-to-send signal, an infrastructure request-to-send signal, or an infrastructure clear-to-send signal, whichever arrives first at the radio data interface,

and the second signal is either an ad-hoc request-to-send signal, an ad-hoc clear-to-send signal, an infrastructure request-to-send signal, or an infrastructure clear-to-send signal, whichever arrives second at the radio data interface.

43. An apparatus according to claim 34, wherein the processing core is a media access control core.

44. The mode control apparatus according to claim 37, wherein the first timeout period is a predetermined period to wait for either an ad-hoc clear-to-send or an ad-hoc request-to-send signal, and

wherein the second timeout period is a predetermined period to wait for one of either an infrastructure clear-to-send or an infrastructure request-to-send signal.

45. Computer-executable process steps stored on a computer-readable medium, the computer-executable process steps comprising:

detecting and processing a first wireless signal and a second wireless signal;

executing a first wireless process, wherein execution of the first wireless process begins upon receipt of the first wireless signal;

executing a second wireless process, wherein execution of the second wireless process begins upon receipt of the second wireless signal,

wherein the first wireless process and the second wireless process are executed separately or concurrently.

46. Computer-executable process steps according to claim 45, further comprising:

a first timeout period and a second timeout period,

wherein execution of the first wireless process begins during the first timeout period and ends after the first timeout period has expired, and

wherein execution of the second wireless process begins during the second timeout period and ends after the second timeout period has expired.

47. A computer-readable medium which stores computer-executable process steps, the computer-executable process steps comprising:

detecting and processing a first wireless signal and a second wireless signal;

executing a first wireless process, wherein execution of the first wireless process begins upon receipt of the first wireless signal;

executing a second wireless process, wherein execution of the second wireless process begins upon receipt of the second wireless signal,

wherein the first wireless process and the second wireless process are executed separately or concurrently.

48. A computer-readable medium according to claim 47, which stores computer-executable process steps, the computer-executable process steps further comprising:

a first timeout period and a second timeout period,

wherein execution of the first wireless process begins during the first timeout period and ends after the first timeout period has expired; and

wherein execution of the second wireless process begins during the second timeout period and ends after the second timeout period has expired.

49. Computer-executable process steps stored on a computer-readable medium, the computer-executable process steps comprising:

a first step for executing a first process or a second process;

a second step for executing a first process or a second process; and

a third step for detecting and processing a first wireless signal and a second wireless signal,

wherein the first step is started and ended for executing either the first wireless signal or the second wireless signal, and wherein the second step is started and ended for executing either the first wireless signal or the second wireless signal

50. Computer-executable process steps according to claim 49, further comprising:

a first timeout period and a second timeout period;

wherein execution of the first wireless process occurs during the first timeout period, and

wherein execution of the second wireless process occurs during the second timeout period.

51. A computer-readable medium which stores computer-executable process steps, the computer-executable process steps comprising:

a first step for executing a first process or a second process;

a second step for executing a first process or a second process; and

a third step for detecting and processing a first wireless signal and a second wireless signal,

wherein the first step is started and ended for executing either the first wireless signal or the second wireless signal, and wherein the second step is started and ended for executing either the first wireless signal or the second wireless signal

52. A computer-readable medium according to claim 51, which stores computer-executable process steps, the computer-executable process steps further comprising:

a first timeout period and a second timeout period;

wherein execution of the first wireless process occurs during the first timeout period, and

wherein execution of the second wireless process occurs during the second timeout period.