High-speed IEEE 1394 link interface

• US 20060050731A1
• Filed: 09/09/2005
• Published: 03/09/2006
• Est. Priority Date: 09/09/2004
• Status: Abandoned Application

• Current Assignee: Christopher Thomas
• Original Assignee: Christopher Thomas
• Inventors: Thomas, Christopher
• Application Number:
  US11/222,703
• Publication Number:
  US 20060050731A1
• Time in Patent Office: Days
• US Class Current: 370/462
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0012 High speed serial bus, e.g. IEEE P1394

Abstract

A High-speed IEEE 1394 Link Interface is disclosed. Also disclosed is an interface device and method that is compatible with legacy IEEE 1394 devices. The device is used to replace a conventional 1394 physical layer interface device and can then cooperatively operate with a slightly modified link layer controller. The device is further selectively activatable and deactivatable. When activated, the device will double the clock speed, and therefore permit data transfer rates of 1600 Megabits per second, with Control Signal transfer speeds of 200 MHz.

Claims

1. A high-speed IEEE 1394 link interface, comprising:

a speed-selectable electrical physical layer device, said electrical physical layer device operational in three selectable speed modes, alpha, beta and fast beta modes; and

a speed-selecting link layer device in communication with said speed-selectable electrical physical layer device, said link layer device controlling said physical layer device to switch between said beta and said fast beta modes.

2. The interface of claim 1, wherein said fast beta mode consists essentially of a clock speed of about 200 megahertz, a data transfer rate of about 1600 megabits per second, and a control signal transfer speed of about 200 megahertz.

3. The interface of claim 2, wherein said alpha mode consists essentially of a clock speed of about 50 megahertz, a data transfer rate of about 400 megabits per second, and a control signal transfer speed of about 50 megahertz.

4. The interface of claim 3, wherein said beta mode consists essentially of a clock speed of about 100 megahertz, a data transfer rate of about 800 megabits per second, and a control signal transfer speed of about 100 megahertz.

5. The interface of claim 4, wherein said physical layer device switches from said beta mode to said fast beta mode upon detection of a set fast beta bit.

6. The interface of claim 5, wherein said fast beta bit status is controlled by said link layer device.

7. The interface of claim 6, wherein said interface is disabled for a predetermined time period when said physical layer device switches from said beta mode to said fast beta mode.

8. The interface of claim 7, wherein said interface is disabled for a predetermined time period when said physical layer device switches from said fast beta mode to said beta mode.

9. A Phy-Link Interface operational method, said Phy-link interface comprising a speed-selectable electrical physical layer device in communication with a speed-selecting link layer device, the method comprising the steps of:

said link layer device setting a BMODE_LINK parameter to “

high”

;

powering up said physical layer device;

programming internal registers of said physical layer device with said link layer device;

enabling said phy-link interface in BETA mode; and

said physical layer device continuously monitoring a FASTBETA bit parameter.

10. The method of claim 9, wherein if said FASTBETA bit parameter is detected as “

set”

, said phy-link interface is disabled for a predetermined data and speed matching period.

11. The method of claim 10, wherein upon expiration of said data and speed matching period, enabling said phy-link interface in FASTBETA mode.

12. The method of claim 11, wherein if said FASTBETA bit parameter is detected as “

not set”

after said phy-link interface is enabled in said FASTBETA mode, said phy-link interface is second disabled for said predetermined data and speed matching period.

13. The method of claim 12, wherein upon expiration of said data and speed matching period of said second disabling, enabling said phy-link interface in said BETA mode.

14. The method of claim 13, wherein said phy-link interface performance parameters when in said BETA mode consist essentially of a clock speed of about 100 megahertz, a data transfer rate of about 800 megabits per second and a control signal speed of about 100 megahertz.

15. The method of claim 14, wherein said phy-link interface performance parameters when in said FASTBETA mode consist essentially of a clock speed of about 200 megahertz, a data transfer rate of about 1600 megabits per second and a control signal speed of about 200 megahertz.

16. A high-speed IEEE 1394 link interface, comprising:

a speed-selectable electrical physical layer device, said electrical physical layer device operational in three selectable speed modes, alpha, beta and fast beta modes; and

a speed-selecting link layer device in communication with said speed-selectable electrical physical layer device, said link layer device controlling said physical layer device to switch between said beta and said fast beta modes.

17. The interface of claim 16, wherein said fast beta mode is defined by a clock speed of about 200 megahertz, a data transfer rate of about 1600 megabits per second, and a control signal transfer speed of about 200 megahertz.

18. The interface of claim 17, wherein said alpha mode is defined by a clock speed of about 50 megahertz, a data transfer rate of about 400 megabits per second, and a control signal transfer speed of about 50 megahertz.

19. The interface of claim 18, wherein said beta mode is defined by a clock speed of about 100 megahertz, a data transfer rate of about 800 megabits per second, and a control signal transfer speed of about 100 megahertz.

20. The interface of claim 19, wherein said physical layer device switches from said beta mode to said fast beta mode upon detection of a set fast beta bit, said fast beta bit status being controlled by said link layer device.