System and method for reducing phase distortion in a linear transmitter via the introduction of bias currents to a power amplifier

• US 20060050809A1
• Filed: 12/17/2004
• Published: 03/09/2006
• Est. Priority Date: 09/03/2004
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pan, Meng-An
• Application Number:
  US11/013,913
• Publication Number:
  US 20060050809A1
• Time in Patent Office: Days
• US Class Current: 375/297
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2203/45361 the AAC comprising multiple transistors parallel coupled at their drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45398 the AAC comprising a voltage generating circuit as bias circuit for the AAC
• CPC Class Codes: H03F 2203/45481 the CSC comprising only a direct connection to the supply voltage, no other components being present
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/604 using FET's

Abstract

The invention decreases phase distortion in a transmitter by balancing C load in the power amplifier input such that a PGA won'"'"'t have phase distortion.

Claims

1. A power amplifier, comprising:

two sets of differential pairs;

a differential inductor coupled to each of the differential pairs;

wherein each of the differential pairs includes a bias transistor supplying a bias voltage to the amplifier that in combination balance the C load; and

wherein a change in current in a bias transistor of one of the differential pairs is independent of current in the other bias transistor.

2. The amplifier of claim 1, wherein output of the pairs are combined.

3. The amplifier of claim 1, wherein the amplifier tunes out parasitic capacitance.

4. The amplifier of claim 1, wherein each pair includes a positive and a negative branch.

5. The amplifier of claim 1, wherein one pair has a bias voltage in Class AB operation while the other pair has a bias voltage close to Class B operation.

6. The amplifier of claim 1, wherein the amplifier includes a plurality current mirrors the enable the independent change of current in a bias transistor.

7. A transmitter having an amplifier according to claim 1.

8. A method, comprising:

presenting a load by two sets of differential pairs of a power amplifier, wherein the pairs are coupled to a differential inductor;

supplying bias voltages to the differential pairs that in combination balance the C load; and

wherein a change in current in a bias transistor of one of the differential pairs is independent of current in the other bias transistor.

9. The method of claim 8, further comprising combining the output of the pairs.

10. The method of claim 8, wherein the amplifier tunes out parasitic capacitance.

11. The method of claim 8, wherein each pair includes a positive and a negative branch.

12. The method of claim 8, wherein one pair has a bias in Class AB operation while the other pair has a bias voltage close to Class B operation.

13. The method of claim 8, wherein the amplifier includes a plurality current mirrors the enable the independent change of current in a bias transistor.