Integrated circuit having clock trim circuitry

• US 20060052962A1
• Filed: 08/29/2005
• Published: 03/09/2006
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Shipton, Gary, Walmsley, Simon Robert
• Granted Patent: US 7,171,323 B2
• Time in Patent Office: Days
• US Class Current: 702/106
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Claims

1. An integrated circuit comprising:

a processor;

an onboard system clock having a ring oscillator for generating a clock signal;

a memory; and

clock trim circuitry, wherein the processor is arranged to;

in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; and

in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

2. An integrated circuit according to claim 1, wherein the memory incorporates non-volatile memory.

3. An integrated circuit according to claim 2, where the non-volatile memory is flash RAM.

4. An integrated circuit according to claim 1, wherein the clock trim circuitry incorporates a register, the processor being arranged to loading the trim value from the memory into register.

5. An integrated circuit according to claim 1, wherein the trim value is stored permanently in the integrated circuit.

6. An integrated circuit according to claim 1, further comprising at least one fuse, the processor being arranged to blow the at least one fuse upon outputting the determined number of cycles to the external circuit, thereby preventing the subsequently received and stored trim value from being changed.

8. An integrated circuit according to claim 1, wherein the integrated circuit is configured to operate under conditions in which the signal for which the number of cycles is being determined is at a considerably higher frequency than the other signal.

9. An integrated circuit according to claim 8, configured to operate when a ratio of the number of cycles determined and the predetermined number of cycles is greater than about 2.

10. An integrated circuit according to claim 9, wherein the ratio is greater than about 4.

11. An integrated circuit according to claim 1, disposed in a package having an external pin for receiving the external signal.

12. An integrated circuit according to claim 11, wherein the pin is a serial communication pin configurable for serial communication when the trim value is being set.

13. An integrated circuit according to claim 1, wherein the trim value is also based on a compensation factor accounting for a temperature of the integrated circuit during the determination of the number of cycles.

7. An integrated circuit according to claim 7, further comprising a digital to analog converter configured to convert the stored trim value to a voltage and supply the voltage to an input of the ring oscillator, thereby to control the frequency of the clock signal generated by the ring oscillator.