Method and system for optimizing DMA channel selection

• US 20060053236A1
• Filed: 09/08/2004
• Published: 03/09/2006
• Est. Priority Date: 09/08/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Gandhi, Rajendra R., Chu, Kuangfu D., Sonksen, Bradley S.
• Granted Patent: US 7,577,772 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

Claims

1. A host bus adapter coupled to a network and a host computing system, comprising:

a direct memory access (“

DMA”

)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data.

2. The host bus adapter of claim 1, wherein the DMA mode detection module includes a register that stores the threshold value and the threshold value is programmable.

3. The host bus adapter of claim 1, wherein the plural DMA channels include a DMA channel in a receive path of the host bus adapter.

4. The host bus adapter of claim 1, wherein the plural DMA channels include a DMA channel in a transmit path of the host bus adapter.

5. The host bus adapter of claim 1, wherein the single channel mode is enabled for a certain duration.

6. The host bus adapter of claim 1, further comprising:

a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

7. A system that allows a host computing system to communicate with plural devices over a network, comprising:

a host bus adapter including a direct memory access (“

DMA”

)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data.

8. The system of claim 7, wherein the DMA mode detection module includes a register that stores the threshold value and the threshold value is programmable.

9. The system of claim 7, wherein the plural DMA channels include a DMA channel in a receive path of the host bus adapter.

10. The system of claim 7, wherein the plural DMA channels include a DMA channel in a transmit path of the host bus adapter.

11. The system of claim 7, wherein the single channel mode is enabled for a certain duration.

12. The system of claim 7, wherein the plural devices include storage devices.

13. The system of claim 7, wherein the network is fibre channel based.

14. The system of claim 7, wherein the host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

15. A host computing system that can communicate with plural devices over a network, comprising:

a host bus adapter operationally coupled to the host computing system includes a direct memory access (“

DMA”

)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data.

16. The host computing system of claim 15, wherein the DMA mode detection module includes a register that stores the threshold value and the threshold value is programmable.

17. The host computing system of claim 15, wherein the plural DMA channels include a DMA channel in a receive path of the host bus adapter.

18. The host computing system of claim 15, wherein the plural DMA channels include a DMA channel in a transmit path of the host bus adapter.

19. The host computing system of claim 15, wherein the single channel mode is enabled for a certain duration.

20. The host computing system of claim 15, wherein the host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

21. A method for transferring data between a host computing system and plural devices using a host bus adapter (“

HBA”

) coupled to a network, comprising;

determining if a same direct memory access (“

DMA”

) channel in the HBA has been exclusively serviced for a certain duration; and

enabling a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data between the host computing system and the plural devices.

22. The method of claim 21, wherein a DMA sequence counter keeps a count of how often the same DMA channel has been serviced by an arbitration module.

23. The method of claim 22, wherein the arbitration module receives requests from plural DMA channels.

24. The method of claim 22, wherein the DMA sequence counter value is compared to a programmable threshold value to determine if the single channel mode should be enabled.

25. The method of claim 24, wherein the programmable threshold value is stored in a register in a DMA mode detection module.