Generic universal serial bus device operable at low and full speed and adapted for use in a smart card device

• US 20060053244A1
• Filed: 09/09/2004
• Published: 03/09/2006
• Est. Priority Date: 09/09/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV), Axalto SA (Thales SA)
• Inventors: Fruhauf, Serge, Leydier, Robert A.
• Granted Patent: US 7,685,328 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Claims

1. A USB device comprising:

a USB transceiver connected to a data interface and operable at a respective low speed and full speed configuration; and

a processor operatively connected to said transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed of operation is chosen.

2. A USB device according to claim 1, and further comprising a Serial Interface Engine operatively connected to said USB transceiver and operable the same in either the low or full speed.

3. A USB device according to claim 1, wherein said processor comprises a microcontroller.

4. A USB device according to claim 1, wherein said processor is operable for allowing the transmission of a GetDescriptor request for uploading a different response depending on the speed of the device.

5. A USB device according to claim 1, wherein said processor is operable for configuring an endpoint0 and control transfer when the low speed USB transceiver is enabled.

6. A USB device according to claim 1, wherein said processor is operative for configuring an endpoint0 and control transfer and operable by the full speed device to send its configuration to a USB host.

7. A USB device according to claim 1, wherein said processor is operable for transferring about 8 bytes maximum in a bidirectional pipe at a low speed of about 6 MHz clock speed.

8. A USB device according to claim 1, wherein said processor is operable for configuring two endpoints In and Out for Bulk transfer of data at irregular intervals.

9. A USB device according to claim 1, and further comprising a clock circuit that switches between a low speed and high speed clock specification.

10. A USB device according to claim 1, wherein said data interface comprises two data interfaces (D+, D−

) and said USB transceiver is operatively connected to said two data interfaces.

11. A USB device according to claim 1, and further comprising a generic application bus through which a device descriptor is uploaded.

12. A USB device according to claim 1, wherein a low speed comprises a default configuration during initial power-on.

13. A USB device according to claim 1, and further comprising a USB device controller and programmable configuration circuit.

14. A USB device according to claim 1, wherein said USB device comprises a smart card.

15. A USB device comprising:

a data interface comprising at least one D+ and D−

terminal;

an integrated pull-up resistor circuit having pull-up resistors operable with respective D+ and D−

terminals;

a low speed USB transceiver and a full speed USB transceiver connected to said data interface and operable at a respective low speed and full speed operation;

a processor; and

a programmable Universal Serial Bus Device controller (UDC) operatively connected to said processor and said low speed USB transceiver and full speed USB transceiver and integrated pull-up resistor circuit and operable together for configuring a low speed operation as a default, disconnecting a pull-up resistor on D−

, connecting a pull-up resistor to D+, and performing an enumeration for high speed operation.

16. A USB device according to claim 15, and comprising a Serial Interface Engine connected to said USB device controller and full speed and low speed transceiver and operable either in the low or full speed.

17. A USB device according to claim 15, wherein said processor is operatively connected to said device controller that allows downloading of programmable configurations to said device controller.

18. A USB device according to claim 15, wherein said microcontroller and processor are operable for allowing the transmission of a GetDescriptor request for uploading a different response depending on the speed of the device.

19. A USB device according to claim 15, wherein said microcontroller and processor are operable for configuring an endpoint0 and control transfer when the low speed USB transceiver is enabled.

20. A USB device according to claim 15, microcontroller and processor are operative for configuring an endpoint0 and control transfer and operable by the full speed device to send its configuration to a USB host.

21. A USB device according to claim 15, wherein said microcontroller and processor are operable for transferring about 8 bytes maximum in a bidirectional pipe at a low speed of about 6 MHz clock speed.

22. A USB device according to claim 15, wherein said microcontroller and processor are operable for configuring two endpoints In and Out for Bulk transfer of data at irregular intervals.

23. A USB device according to claim 15, wherein said bulk transfer of data is about 64 bytes maximum at about 48 MHz clock speed.

24. A USB device according to claim 15, wherein said data interface comprises two data interfaces (D+, D−

) and said low speed transceiver and full speed transceiver are operatively connected to said two data interfaces.

25. A USB device according to claim 15, and further comprising a generic application bus through which a device descriptor is uploaded.

26. A USB device according to claim 15, wherein a low speed is a default configuration during initial power-on.

27. A USB device according to claim 15, and further comprising a clock circuit having a programmable source for switching from a low speed clock specification to a full speed clock specification.

28. A USB device according to claim 15, wherein said USB device comprises a smart card.

29. An integrated circuit for a USB device comprising:

a data interface;

a USB transceiver connected to a data interface and operable at a respective low speed and full speed operation;

a serial interface engine operative with the USB transceiver for translating packets of serial USB bitstream into parallel data; and

a processor operatively connected to said serial interface engine and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed of operation is chosen.

30. An integrated circuit according to claim 29, wherein said data interface comprises at least one D+ and D−

terminal, and further comprising an integrated pull-up resistor circuit having pull-up resistors operable with respective D+ and D−

terminals and operable for configuring a low speed operation as a default, disconnecting a pull-up resistor on D−

, connecting a pull-up resistor to D+, and transmitting a different device descriptor to a USB host for performing an enumeration for high speed operation.

31. An integrated circuit according to claim 29, and further comprising a processor that is operable the same in either low or full speed.

32. An integrated circuit according to claim 29, wherein said processor comprises a microcontroller.

33. An integrated circuit according to claim 29, wherein said processor is operable for allowing the transmission of a GetDescriptor request for uploading a different response depending on the speed of the device.

34. An integrated circuit according to claim 29, wherein said processor is operable for configuring an endpoint0 and control transfer when the low speed of the USB transceiver is enabled.

35. An integrated circuit according to claim 29, wherein said processor is operative for configuring an endpoint0 and control transfer and operable at full speed to send its configuration to a USB host.

36. An integrated circuit according to claim 29, wherein said processor is operable for transferring about 8 bytes maximum in a bidirectional pipe at low speed.

37. An integrated circuit according to claim 29, wherein said processor is operable for configuring two endpoints In and Out for Bulk transfer of data at irregular intervals.

38. An integrated circuit according to claim 29, wherein said bulk transfer of data is about 64 bytes maximum.

39. An integrated circuit according to claim 29, wherein said data interface comprises two data interfaces (D+, D−

) and said USB transceiver is operatively connected to said two data interfaces.

40. An integrated circuit according to claim 29, and further comprising a generic application bus through which a device descriptor is uploaded.

41. An integrated circuit according to claim 29, wherein a low speed is a default configuration during initial power-on.

42. An integrated circuit according to claim 29, and further comprising a clock circuit having a programmable source for switching from a low speed clock specification to a full speed clock specification.

43. An integrated circuit according to claim 29, wherein said USB device comprises a smart card.

44. A method of operating a USB device comprising the step of:

transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed of operation is chosen.

45. A method according to claim 44, and further comprising the step of transmitting a GetDescriptor request for uploading a different response depending on the speed of the device.

46. A method according to claim 44, and further comprising the step of configuring an endpoint0 and control transfer when the low speed USB transceiver is enabled.

47. A method according to claim 44, and further comprising the step of configuring an endpoint0 and control transfer for sending a configuration to a USB host during high speed operation.

48. A method according to claim 44, and further comprising the step of configuring two endpoints In and Out for Bulk transfer of data at irregular intervals.

49. A method according to claim 44, and further comprising the step of updating a device descriptor through a generic application bus.

50. A smart card comprising:

a smart card body;

contacts carried by said smart card body;

an integrated circuit carried by said smart card body and comprising a data interface operable with said contacts;

a USB transceiver connected to said data interface and operable at a respective low speed and full speed configuration; and

a processor operatively connected to said USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed of operation is chosen.

51. A smart card according to claim 50, wherein said data interface comprises at least one D+ and D−

terminal, and further comprising an integrated pull-up resistor circuit having pull-up resistors operable with respective D+ and D−

terminals and operable for configuring a low speed operation as a default, disconnecting a pull-up resistor on D−

, connecting a pull-up resistor to D+, and transmitting a different device descriptor to a USB host for performing an enumeration for high speed operation.

52. A smart card according to claim 50, wherein said contacts on said card body are operable configured in accordance with ISO standards.

53. A smart card according to claim 50, and further comprising a serial interface engine operatively connected to said USB transceiver and operable the same in either the low or full speed operation.

54. A smart card according to claim 50, wherein said processor comprises a microcontroller.

55. A smart card according to claim 50, wherein said processor is operable for allowing transmission of a GetDescriptor request for uploading a different response depending on speed.

56. A smart card according to claim 50, wherein said processor is operable for configuring an endpoint0 and control transfer when the low speed USB transceiver is enabled.