Systems and methods for providing nonvolatile memory management in wireless phones

• US 20060053246A1
• Filed: 08/30/2005
• Published: 03/09/2006
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Lee, Schweiray Joseph
• Granted Patent: US 7,475,184 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.

Claims

1. A wireless phone memory controller, comprising:

a nonvolatile memory controller circuit configured to be coupled to nonvolatile memory;

a volatile memory controller circuit configured to be coupled to volatile memory;

a boot controller circuit configured to be coupled to the nonvolatile memory controller circuit, the boot controller circuit configured to cause user-defined boot program code to be read from nonvolatile memory into memory controller memory;

a first processor interface, including a first reset signal, configured to be coupled to a first wireless phone processor, wherein, the memory controller is configured to release the first wireless phone processor from a reset state after the user-defined boot code is read into the memory controller memory; and

a second processor interface, including a second reset signal, configured to be coupled to a second wireless phone processor, wherein the second reset signal is configured to be controlled at least in part by the first processor.

2. The wireless phone memory controller as defined in claim 1, further comprising:

a first display interface configured to be coupled to a first display; and

a second display interface configured to be coupled to a second display wherein, the memory controller is further configured to transfer display data from the volatile memory to at least the second display at least partly in response to receiving a memory transfer request from the first processor.

3. The wireless phone memory controller as defined in claim 1, further comprising an interface configured to be coupled to a removable memory device.

4. The wireless phone memory controller as defined in claim 1, further comprising an interface configured to be coupled to a removable memory card.

5. The wireless phone memory controller as defined in claim 1, wherein the user defined boot code is loaded into dedicated boot volatile memory.

6. The wireless phone memory controller as defined in claim 1, wherein the nonvolatile memory includes NAND Flash memory.

7. The wireless phone memory controller as defined in claim 1, wherein the nonvolatile memory includes AND Flash memory.

8. The wireless phone memory controller as defined in claim 1, wherein the volatile memory includes SDRAM memory.

9. The wireless phone memory controller as defined in claim 1, further comprising:

a DMA controller configured to transfer data from the nonvolatile to the volatile memory in response to a request received via the first processor port; and

an ECC circuit configured to provide error detection and correction of data read from the nonvolatile memory.

10. The wireless phone memory controller as defined in claim 1, further comprising memory storing user defined Flash media management code.

11. The wireless phone memory controller as defined in claim 1, further comprising a data buffer used to buffer data with respect to nonvolatile data transfers.

12. The wireless phone memory controller as defined in claim 1, further comprising an error detection and correction circuit that can detect and correct at least a portion of data errors in data read from nonvolatile memory without the intervention of the first or second processors.

13. The wireless phone memory controller as defined in claim 1, further comprising a circuit that copies a plurality of data pages from nonvolatile memory to volatile memory without intervention of the first or second processors.

14. The wireless phone memory controller as defined in claim 1, further comprising a second nonvolatile memory controller and a second volatile memory controller.

15. A method of transferring data from wireless phone nonvolatile memory, the method comprising:

after a power-on reset, generating a first address using a boot circuit;

accessing data from the wireless phone'"'"'s nonvolatile Flash memory, including at least data stored at the first address;

storing the accessed data in a page buffer;

determining whether the accessed data is boot code or Flash memory management code;

if the accessed data is boot code, copying the data from the page buffer to a boot random access memory; and

if the accessed data is Flash memory management code, copying the data from the page buffer to Flash memory management random access memory.

16. The method as defined in claim 15, further comprising holding a first modem processor in reset while performing Flash memory management initialization using the Flash memory management code stored in the Flash memory management buffer.

17. The method as defined in claim 16, further comprising releasing the modem processor from reset.

18. The method as defined in claim 17, further comprising providing a data path via which the modem processor can execute the boot code stored in the boot random access memory.

19. A wireless phone memory controller, comprising:

a first interface circuit configured to be coupled to wireless phone nonvolatile memory;

a second interface circuit configured to be coupled to wireless phone volatile memory;

a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory;

a second processor interface configured to be coupled to a second wireless phone processor; and

a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory without intervention by the first processor or the second processor.

20. The wireless phone memory controller as defined in claim 19, wherein the controller circuit configured to write data from the first wireless phone processor into the wireless phone nonvolatile memory.

21. The wireless phone memory controller as defined in claim 19, wherein the volatile memory is Flash memory, and further comprising a circuit configured to execute Flash memory management processes without the intervention of the first or second processors.

22. The wireless phone memory controller as defined in claim 19, wherein the first phone processor and the second processor provide logical addresses to the controller circuit when accessing the nonvolatile memory, and the controller circuit is configured to perform logical to physical address translation to be used when accessing the nonvolatile memory in response to a request from the first or second phone processors.

23. The wireless phone memory controller as defined in claim 19, wherein the controller circuit is configured to automatically perform user defined tasks in accordance with a user-defined sequence prior to waking up the first processor after a power-on reset, including:

loading Flash media management code from the wireless phone nonvolatile memory to a Flash memory manager circuit'"'"'s local memory after a power-on reset; and

performing a security check or data stored in the wireless phone nonvolatile memory.

24. The wireless phone memory controller as defined in claim 19, further comprising a control circuit configured to transfer boot program code from the wireless phone nonvolatile memory to boot volatile memory, wherein the first processor interface further comprises a reset signal configured to hold the first processor in a reset state while at least a portion of the boot program code is being transferred into the boot volatile memory.

25. The wireless phone memory controller as defined in claim 19, wherein the wireless phone nonvolatile memory is configured to be accessed in a page mode.

26. The wireless phone memory controller as defined in claim 19, further comprising an error correction and detection circuit configured to detect and correct errors with respect data read from the wireless phone nonvolatile memory.

27. The wireless phone memory controller as defined in claim 19, further comprising the wireless phone nonvolatile memory, wherein the memory controller and the wireless phone nonvolatile memory are housed in a single device package, wherein access to the wireless phone nonvolatile memory is controlled by the memory controller to thereby prevent unauthorized access to the nonvolatile memory.

28. A method of operating a wireless phone memory circuit, the method comprising:

deasserting a reset signal;

generating a first address corresponding to boot data stored in wireless phone nonvolatile memory;

reading boot program code from the wireless phone nonvolatile memory beginning at the first address;

providing error detection with respect to the boot program code;

correcting at least a first error if a first error is detected;

loading the boot code, including corrected boot code if such is present, into volatile random access memory;

loading Flash memory management program code from the wireless phone nonvolatile memory into Flash memory management volatile memory;

enabling the Flash memory management program code to be executed by a Flash memory management circuit;

releasing a first wireless phone processor, coupled to the wireless phone memory circuit, from a reset state;

providing the first wireless phone processor with access to the boot program code; and

providing a second wireless phone processor with access to code stored in the volatile memory.

29. The method as defined in claim 28, further comprising:

enabling the first wireless phone processor to load at least a first memory configuration circuit with a first set of information; and

transferring program code from the nonvolatile memory to the volatile memory at least partly in response to a command from the first wireless phone processor and the first set of information, wherein the first wireless phone processor executes at least a first program stored in the volatile memory.

30. The method as defined in claim 28, further comprising:

receiving a display write command from the first wireless phone processor;

generating a first volatile memory address; and

copying data from the volatile memory beginning at the first address to a first wireless phone display.

31. The method as defined in claim 28, further comprising transferring display data from volatile random access memory to a first phone display and a second phone second display.

32. A method of performing error correction on data stored or being stored in a wireless phone'"'"'s nonvolatile memory, the method comprising:

receiving a first page of data configured to be stored in a wireless phone nonvolatile memory, the first page including user data stored in a user portion and spare data stored in a spare portion;

generating page parity data for the first page of data;

storing the page parity data in the wireless phone nonvolatile memory;

storing spare data in the wireless phone nonvolatile memory, wherein the spare data includes bookkeeping data for nonvolatile memory management and/or system flags;

generating and storing parity data for the spare data in the wireless phone nonvolatile memory;

reading the spare data from the wireless phone nonvolatile memory;

reading the parity data for the spare data from the wireless phone nonvolatile memory; and

performing error detection and error correction, if needed, on the spare data from the wireless phone nonvolatile memory using the spare data parity information.

33. The method as defined in claim 32, wherein parity data is calculated using a Reed-Solomon Code.

34. The method as defined in claim 32, wherein parity data is calculated using a Hamming Code.

35. A wireless phone memory system, comprising:

a first port coupled to wireless phone nonvolatile memory;

a second port circuit coupled to wireless phone volatile memory;

a first processor interface coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory; and

a second processor interface coupled to a second wireless phone processor,

wherein one of the first and second processors is configured to provide modem control.

36. The wireless phone memory controller as defined in claim 35, further comprising a control circuit that transfers boot program code from the wireless phone nonvolatile memory to boot volatile memory, wherein the first processor interface further comprises a reset signal configured to hold the first processor in a reset state while at least a portion of the boot program code is being transferred into the boot volatile memory.

37. The wireless phone memory controller as defined in claim 35, further comprising a memory card interface configured to be coupled to a removable memory card.

38. The wireless phone memory controller as defined in claim 35, further comprising an interface configured to be coupled to one or more of a Memory Stick card, a Smart Media card, a Secure Digital card, a CompactFlash card, or a MultiMedia card.

39. The wireless phone memory controller as defined in claim 35, further comprising a direct memory access circuit configured to transfer data from the wireless phone nonvolatile memory to the wireless phone volatile memory without intervention of the first or the second processor once the transfer has begun.

40. The wireless phone memory controller as defined in claim 35, further comprising a memory access circuit configured to selectively grant memory access to a plurality of requesters.

41. A wireless phone memory system, comprising:

a first port coupled to wireless phone nonvolatile memory;

a second port circuit coupled to wireless phone volatile memory;

a first device interface coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory; and

a second device interface selectively configurable to be coupled to a second wireless phone processor or a wireless phone display.

42. The wireless phone memory controller as defined in claim 41, further comprising a control circuit that transfers boot program code from the wireless phone nonvolatile memory to boot volatile memory, wherein the first processor interface further comprises a reset signal configured to hold the first processor in a reset state while at least a portion of the boot program code is being transferred into the boot volatile memory.

43. The wireless phone memory controller as defined in claim 41, further comprising a memory card interface configured to be coupled to a removable memory card.

44. The wireless phone memory controller as defined in claim 41, further comprising a third device interface configured to be coupled to at least one wireless phone processor.

45. The wireless phone memory controller as defined in claim 41, further comprising a direct memory access circuit configured to transfer data from the wireless phone nonvolatile memory to the wireless phone volatile memory without intervention of the first processor once the transfer has begun.

46. The wireless phone memory controller as defined in claim 41, further comprising a memory access circuit configured to selectively grant memory access to a plurality of requesters.

47. The wireless phone memory controller as defined in claim 41, further comprising a memory element intended to store a starting display address, a starting volatile memory address, and an indication as to how much data is to be transferred from the volatile memory address to the display.

48. A wireless phone memory controller device, comprising:

a first port configured to be coupled to wireless phone nonvolatile memory;

a second port circuit configured to be coupled to a modem processor of a wireless phone;

a volatile boot memory;

a boot controller configured to copy boot code from the wireless phone nonvolatile memory to the volatile boot memory;

a direct memory access controller configured to copy data from the nonvolatile memory to the volatile boot memory in response to a command from the modem processor; and

providing a path via which the modem processor can read boot memory data.

49. The wireless phone memory controller as defined in claim 48, wherein the first port further includes an error correction and detection circuit configured to detect errors with respect to data read from the wireless phone nonvolatile memory and to correct at least a portion of detected errors.

50. The wireless phone memory controller as defined in claim 48, wherein the first port further includes data buffer, intended to accommodate a mismatch between a data transfer rate of the first port and a data transfer rate of the second port.

51. The wireless phone memory controller as defined in claim 48, further comprising a memory card interface configured to be coupled to a removable memory card.

52. The wireless phone memory controller as defined in claim 48, further comprising a third port configured to be coupled to at least one wireless phone processor.

53. A method of operating a wireless phone memory system so as to protect data stored in writable nonvolatile memory from being overwritten, the method comprising:

receiving at a memory control circuit a write command from a first wireless phone processor, wherein the write command indicates that a write operation is to be performed to wireless phone nonvolatile memory;

receiving at the memory control circuit a first logical address from the first wireless phone processor, corresponding to the first logical address to which data is to be written to;

translating at a wireless phone memory control circuit the first logical address to a first physical address, wherein the first physical address is selected at least in part to avoid at least a first protected area of the wireless phone nonvolatile memory, so as to prevent the first protected area from being overwritten; and

writing data as instructed by the first wireless phone processor to the first physical address at least partly in response to the write command.

54. The method as defined in claim 53, wherein the first protected area stores memory management code.

55. The method as defined in claim 53, wherein the first protected area is defined by code stored in the wireless phone nonvolatile memory, the code defining the first protected area in terms of logical address, physical address or both.

56. The method as defined in claim 53, wherein the first wireless phone processor provides modem functions.

57. A wireless phone memory controller, comprising:

a first interface circuit configured to be coupled to wireless phone nonvolatile memory;

a first processor interface configured to be coupled to a first wireless phone processor; and

a controller circuit coupled to the first interface circuit and the first processor interface, the controller circuit configured to receive logical addresses for the wireless phone nonvolatile memory via the first processor interface, and to translate the logical addresses into physical addresses so that the first wireless phone processor does not need to know the physical addresses for at least a subset of code or data stored in the wireless phone nonvolatile memory in order to access the subset of code or data, wherein the physical addresses are used to access code or data stored in the wireless phone nonvolatile memory.

58. The wireless phone memory controller as defined in claim 57, further comprising Flash memory management code stored in computer readable memory, wherein the Flash memory management code is not dependent of the type of first wireless phone processor that will be coupled to the first processor interface.

59. The wireless phone memory controller as defined in claim 57, further comprising a volatile memory interface coupled to the controller circuit, the volatile memory interface configured to be coupled to volatile main memory.

60. The wireless phone memory controller as defined in claim 57, further comprising a second processor interface coupled to the controller circuit and configured to be coupled to a second wireless phone processor.

61. The wireless phone memory controller as defined in claim 57, further comprising:

boot volatile memory; and

a control circuit configured to transfer boot program code from the wireless phone nonvolatile memory to the boot volatile memory, wherein the first processor interface further comprises a reset signal configured to hold the first processor in a reset state while at least a portion of the boot program code is being transferred into the boot volatile memory.

62. The wireless phone memory controller as defined in claim 57, further comprising the wireless phone nonvolatile memory, wherein the memory controller and the wireless phone nonvolatile memory are housed in a single device package, wherein access to the wireless phone nonvolatile memory is controlled by the memory controller to thereby prevent unauthorized access to the nonvolatile memory.

63. The wireless phone memory controller as defined in claim 57, wherein the volatile memory is Flash memory, and further comprising a circuit configured to execute Flash memory management processes without the intervention of the first wireless phone processor.