Apparatus and method for retrieving data from a data storage system

• US 20060053255A1
• Filed: 06/02/2005
• Published: 03/09/2006
• Est. Priority Date: 09/08/2004
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sugizaki, Go
• Application Number:
  US11/142,358
• Publication Number:
  US 20060053255A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration

Abstract

In a memory controller such as a system controller including a level-3 cache memory for common use of data with a level-2 cache memory within a CPU by forming a chip set such as a server, an effective memory controller and a control method are realized to store the necessary data into the level-2 cache memory of the CPU with a single access, thereby reducing or eliminating deterioration of performance and suppression of throughput caused by memory latency.

Claims

1. A memory controller connected to at least one CPU including a first cache memory and a main memory to execute a process for a read request from any CPU, said controller comprising:

a second cache memory; and

a control block respectively issuing a read request to a storing area of a data block within the first cache memory or the second cache memory as an object of the read request and a storing area of other data block included in an entry to which the data block belongs.

4. The memory controller described in claim 1, wherein the control block receives a plurality of data blocks transmitted respectively from a plurality of storing areas and transmits the data block to the CPU by merging a plurality of received data blocks into one data block.

5. The memory controller described in claim 1, wherein the memory controller merges, when at least one data block among other data blocks included in an entry to which the at least one data block corresponding to the read request issued from the at least one CPU connected in direct is stored into the second cache memory, the data blocks transmitted from a plurality of storing areas into one entry and then transmit said entry to the at least one CPU.

2. A memory controller connected to at least one CPU including a first cache memory and a main memory to execute a process for a read request from any CPU, said controller comprising:

a second cache memory; and

a control block for comparing a valid status of a data block in the first and said second cache memories with the read request from any CPU and issuing a read request to respective storing areas when the data block for the read request and other data blocks included in an entry to which a relevant data block belongs and stored into a plurality of storing areas.

3. A memory controller connected to at least one CPU including a first cache memory and a main memory to execute a process for a read request from any CPUs, said controller comprising:

a second cache memory;

a first tag memory storing a valid status of each data block included in the first cache memory to which a CPU belongs;

a second tag memory storing the valid status of each data block included in the second cache memory; and

a control block comparing contents of the first and said second tag memories with a read request from any CPU and issuing a read request to respective storing areas when the data block corresponding to the read request and other data blocks included in an entry to which a relevant data block belongs are stored into a plurality of storing areas included within the first and second cache memories.

6. An information processor, comprising:

at least one CPU;

a first cache memory provided to the CPU to include a plurality of entries formed of a plurality of data blocks;

a main memory;

at least one memory controller for processing read requests from the CPU; and

a second cache memory provided to the memory controller to include a plurality of entries formed of a plurality of data blocks; and

wherein the memory controller issues a read request to respective storing areas within the first or said second cache memories when a data block corresponding to the read request and other data blocks included in an entry to which a relevant data block belongs are scattered and stored into a plurality of storing areas.

7. The information processor described in claim 6, further comprising:

a plurality of memory controllers, and

wherein one memory controller inspects, when a read request is issued from the CPU connected to other memory controllers, a storing area of a data block corresponding to a relevant request by comparing a valid status of the data block in the first and second cache memories with the read request from the CPU connected to other memory controllers, and transmits the data block to the other memory controllers when a result of inspection proves that the data block and at least one data block among the other data blocks included in an entry to which the data block belongs are stored into the first cache memory provided to the CPU connected to the memory controller or to the second cache memory provided in the memory controller.

8. The information processor described in claims 6, characterized in that the memory controller receives a data block respectively transmitted from a plurality of storing areas within the first and said second cache memories and corresponding to a read request issued therefrom and merges a plurality of received data blocks into an entry for transmission to the CPU.

11. The information processor described in claim 6, wherein, when at least one data block among a valid data corresponding to the read request issued from the CPU connected in direct to the memory controller is stored in the cache memory of the memory controller, the data block and the data blocks transmitted from a plurality of storing areas are transmitted to the CPU by merging these data blocks into one entry with the memory controller.

12. The information processor described in claim 6, wherein the memory controller includes a second pipeline for inspecting a storing area of valid data corresponding to the read request by comparing contents of first and second tag memories with the read request issued from the CPU connected in direct to other memory controllers via a data transmission path, and the memory controller transmits the data block to the other memory controllers when a result of inspection proves that at least one data block among the valid data corresponding to the read request is stored in the cache memory of a local memory controller.

9. A memory control method for a memory controller to execute a read request at least from one CPU, comprising:

receiving the read request issued from any CPU;

comparing a valid status of a data block included in a cache memory within the CPU and the valid status of the data block included in the cache memory within the memory controller with the read request; and

issuing the read request to respective storing areas within the first or second cache memories when a comparison result proves that the data block corresponding to the read request and other data blocks included in an entry to which a relevant data block belongs are scattered and stored into a plurality of storing areas.

10. The memory control method described in claim 9, further comprising:

receiving the data blocks respectively transmitted from a plurality of storing areas within the first or second cache memories and corresponding to the read request issued from the memory controller; and

transmitting a plurality of received data blocks to the CPU by merging such data blocks into one entry.

13. A memory controller connected to at least one CPU and a main memory and also connected to other memory controllers via a data transmission path and including a first cache memory in which an entry is formed of a plurality of data blocks and a first tag memory for storing a valid flag of data blocks in order to execute a read request from the CPU in a unit of a data block or entry, a second tag memory for storing, by a copying process, contents of tag memory included in all CPUs connected in direct and a first pipeline for inspecting storing area of the valid data corresponding to a read request by comparing the contents of the first and said second tag memories with the read request issued from any CPU connected in direct, wherein the read request is issued to respective storing areas when a inspection result proves that the data block corresponding to the read request and the other data blocks included in an entry to which a relevant data block belongs are scattered and stored into a plurality of storing areas.

14. A method for retrieving data from a layered data storage system, comprising:

reading data blocks from a main data storage area included within the system only when said blocks are absent or invalid in any other data storage area.

15. A method for retrieving data from a layered data storage system, comprising:

receiving a request to read an entry included within a data block containing valid and invalid entries, wherein at least one valid entry is stored in a data storage area different from a data storage area of at least one invalid entry;

reading said invalid entries from a first storage area to convert said invalid entries to valid; and

merging said converted entries with valid entries from a second storage area.

16. The method of claim 15, wherein said reading includes determining valid and invalid entries via status tags.

17. The method of claim 15, wherein said reading includes reading said invalid entries from a first data storage area wherein said first storage area is a main memory.

18. The method of claim 15, wherein said reading includes reading said valid entries from a second data storage area wherein said second data storage area is a third cache memory.

19. An apparatus for allowing effective memory control, comprising:

a unit merging a valid entry included within a data block of a first data storage area with a previously invalid entry retrieved from a second data storage area.

20. The apparatus of claim 19, wherein the first data storage area is a third cache memory included within a system controller residing on a circuit board a same as a circuit board on which said central processing resides.

21. The apparatus of claim 20, wherein said second data storage area is a main memory.

22. The apparatus of claim 19, wherein said first data storage area is a third cache memory residing on a circuit board different than a circuit board on which said central processing unit resides.

23. The apparatus of claim 19, wherein said unit is a data-reply control block.

24. A data buffer, comprising:

a data block representing an entry having a valid status; and

a data block representing an entry having an invalid status.