Flash EEPROM with metal floating gate electrode

• US 20060054943A1
• Filed: 09/14/2004
• Published: 03/16/2006
• Est. Priority Date: 09/14/2004
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc., Infineon Technologies AG
• Original Assignee: Advanced Micro Devices, Inc., Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Li, Hong-Jyh, Gardner, Mark
• Granted Patent: US 7,138,680 B2
• Time in Patent Office: Days
• US Class Current: 257/266
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.

Claims

1. A memory device comprising:

a substrate including isolation regions and active regions;

a floating gate stack proximate the substrate, the floating gate stack comprising;

a first high-k dielectric layer proximate the substrate;

a first metal layer proximate the first high-k dielectric layer; and

a second high-k dielectric layer proximate the first metal layer; and

a control gate electrode proximate the floating gate stack.

40. The memory device of claim 1, wherein the first high-k dielectric layer is incorporated with N, and wherein the second high-k dielectric layer is incorporated with N.

2. A memory device comprising:

a substrate including isolation regions and active regions;

a floating gate stack proximate the substrate, the floating gate stack comprising;

a first high-k dielectric layer proximate the substrate;

a first metal layer proximate the first high-k dielectric layer;

a second high-k dielectric layer proximate the first metal layer;

a second metal layer proximate the second high-k dielectric layer; and

a third high-k dielectric layer proximate the second metal layer; and

a control gate electrode proximate the floating gate stack.

3. The memory device of claim 2, wherein the floating gate stack further comprises:

a third metal layer proximate the third high-k dielectric layer; and

a fourth high-k dielectric layer proximate the third metal layer.

4. The memory device of claim 2, wherein the second high-k dielectric layer comprises at least one of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

5. The memory device of claim 4, wherein the second high-k dielectric layer is incorporated with N.

6. The memory device of claim 4, wherein the second high-k dielectric layer comprises a mixture comprising at least one of TiN, HfN, TaN, ZrN, and LaN.

7. The memory device of claim 2, wherein the first high-k dielectric layer has a thickness within a range of 1 Å

to 50 Å

.

8. The memory device of claim 2, wherein the first metal layer comprises one of TiN, HfN, TaN, ZrN, and LaN.

9. The memory device of claim 2, wherein the first metal layer has a thickness within a range of 1 Å

to 50 Å

.

10. The memory device of claim 2, wherein the first high-k dielectric layer and the second high-k dielectric layer comprise similar materials.

11. The memory device of claim 2, wherein the first high-k dielectric layer and the second high-k dielectric layer comprise different materials.

12. The memory device of claim 2, wherein the floating gate stack has a thickness within a range of 20 Å

to 500 Å

.

13. The memory device of claim 2, wherein the first metal layer is partially oxidized and the first high-k dielectric layer and the second high-k dielectric layer are incorporated with N from the oxidation.

14. An electrically-erasable programmable read-only memory comprising:

a plurality of memory cells formed on a substrate, each memory cell comprising;

isolation regions and active regions in the substrate;

a floating gate stack proximate the substrate, the floating gate stack comprising;

a first high-k material layer proximate the substrate;

a first metal floating gate electrode proximate the first high-k material layer; and

a second high-k material layer proximate the first metal floating gate electrode; and

a control gate electrode proximate the floating gate stack.

41. The memory device of claim 14, wherein the first high-k material layer is incorporated with N, and wherein the second high-k material layer is incorporated with N.

15. An electrically-erasable programmable read-only memory comprising:

a plurality of memory cells formed on a substrate each memory cell comprising;

isolation regions and active regions in the substrate;

a floating gate stack proximate the substrate, the floating gate stack comprising;

a first high-k material layer proximate the substrate;

a first metal floating gate electrode proximate the first high-k material layer;

a second high-k material layer proximate the first metal floating gate electrode;

a second metal floating gate electrode proximate the second high-k material layer; and

a third high-k material layer proximate the second metal floating gate electrode; and

a control gate electrode proximate the floating gate stack.

16. The memory of claim 15, wherein the first high-k material layer and the second high-k material layer comprise similar high-k materials.

17. The memory of claim 15, wherein the first high-k material layer and the second high-k material layer comprise different high-k materials.

18. The memory of claim 15, wherein the first high-k material layer comprises one of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

19. The memory of claim 18, wherein the first high-k material layer comprises a mixture of at least two of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

20. The memory of claim 18, wherein the first high-k material layer comprises a mixture comprising at least one of TiN, HfN, TaN, ZrN, and LaN.

21. The memory of claim 18, wherein the second high-k material layer comprises one of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

22. The memory of claim 21, wherein the third high-k material layer comprises one of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

23. The memory of claim 15, wherein the first metal floating gate electrode comprises one of TiN, HfN, TaN, ZrN, and LaN.

24. The memory of claim 23, wherein the second metal floating gate electrode comprises one of TiN, HfN, TaN, ZrN, and LaN.

25. A method of making a memory device, the method comprising:

forming isolation regions, well regions, and active regions on a substrate;

depositing a first high-k material layer on the substrate;

depositing a first metal layer on the first high-k material layer; and

depositing a second high-k material layer on the first metal layer;

42. The method of claim 25, wherein depositing the first high-k material layer comprises depositing a first high-k material layer incorporated with N, and wherein depositing the second high-k layer material layer comprises depositing a second high-k material layer incorporated with N.

26. A method of making a memory device, the method comprising:

forming isolation regions, well regions, and active regions on a substrate;

depositing a first high-k material layer on the substrate;

depositing a first metal layer on the first high-k material layer;

depositing a second high-k layer material layer on the first metal layer;

depositing a second metal layer on the second high-k material layer; and

depositing a third high-k material layer on the second metal layer.

27. The method of claim 26, wherein depositing the second high-k dielectric layer comprises simultaneously depositing at least two of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, Zro₂, ZrSiO, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, PMN, TiN, HfN, TaN, ZrN, and LaN.

28. The method of claim 26, further comprising:

annealing the substrate, the first high-k material layer, the first metal layer, the second high-k material layer, the second metal layer, and the third high-k material layer to partially oxidize the first metal layer and the second metal layer.

29. The method of claim 28, further comprising:

depositing a gate electrode material layer on the third high-k material layer.

30. The method of claim 26, further comprising:

depositing a third metal layer on the third high-k material layer; and

depositing a fourth high-k material layer on the third metal layer.

31. The method of claim 26, wherein the first high-k material layer is deposited using atomic layer deposition.

32. The method of claim 26, wherein the first high-k material layer is deposited using one of metal-organic chemical vapor deposition, plasma vapor deposition, and jet vapor deposition.

33. The method of claim 26, wherein the first metal layer is deposited using atomic layer deposition.

34. The method of claim 26, wherein the first metal layer is deposited using one of metal-organic chemical vapor deposition, plasma vapor deposition, and jet vapor deposition.

35. The method of claim 30, further comprising:

depositing a gate electrode material layer on the fourth high-k material layer.

36. The method of claim 26, wherein depositing the first high-k dielectric material layer comprises depositing at least one of Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST, PST, PZN, PZT, and PMN.

37. The method of claim 26, wherein depositing the first metal layer comprises depositing at least one of TiN, HfN, TaN, ZrN, and LaN.

38. The method of claim 37, further comprising:

annealing the substrate, the first high-k material layer, the first metal layer, the second high-k material layer, the second metal layer, and the third high-k material layer to partially oxidize the first metal layer and the second metal layer to incorporate N into the first high-k material layer, the second high-k material layer, and the third high-k material layer.

39. A flash memory device comprising:

a plurality of memory cells formed on a substrate, each memory cell comprising;

isolation regions and active regions in the substrate;

a floating gate stack proximate the substrate, the floating gate stack comprising;

a first high-k material layer proximate the substrate;

a first metal floating gate electrode proximate the first high-k material layer;

a second high-k material layer proximate the first metal floating gate electrode;

a second metal floating gate electrode proximate the second high-k material layer; and

a third high-k material layer proximate the second metal floating gate electrode; and

a control gate electrode proximate the floating gate stack.