DRAM cell having MOS capacitor

• US 20060054955A1
• Filed: 11/03/2005
• Published: 03/16/2006
• Est. Priority Date: 12/16/2002
• Status: Abandoned Application

• Current Assignee: Chung Cheng Holdings LLC (Intellectual Ventures LLC)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Hak-yun
• Application Number:
  US11/265,852
• Publication Number:
  US 20060054955A1
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a plate node electrode which is a part of the active region, a storage node electrode having a T-shaped structure through a trench of the active region and an insulator thin film formed between the plate node electrode and the storage node electrode; a cell transistor having a gate insulating film and a gate electrode which are formed on the top surface of the active region and a source/drain formed within the active region; an interlayer insulating film deposited on a structure with the MOS capacitor and the cell transistor; a contact electrode connected with the source/drain of the cell transistor or with the storage node electrode of the MOS capacitor through a contact hole of the interlayer insulating film; a wire connected with the drain and the storage node electrode through the contact electrode; and a bit line connected with the source through the contact electrode.

Claims

1. A DRAM cell comprising:

A semiconductor substrate comprising an active region,

a word line driven by a row address;

a bit line driven by a column address;

a cell transistor having a source connected to the bit line and a gate electrode connected to the word line; and

a MOS capacitor comprising a storage node electrode connected to a drain of the cell transistor, a plate node electrode formed on the active region of the semiconductor substrate and an insulator thin film formed between the storage node electrode and the plate node electrode.

2. The DRAM cell of claim 1, wherein the storage node electrode has a T-shaped structure through a trench of the active region.

3. The DRAM cell of claim 1, further comprising a power line supplying a power voltage to the plate node electrode.

4. A DRAM cell comprising:

a semiconductor substrate comprising an active region;

a MOS capacitor comprising a plate node electrode disposed in the active region, a storage node electrode having a T-shaped structure through a trench of the active region and an insulator thin film formed between the plate node electrode and the storage node electrode;

a cell transistor comprising a gate insulating film and a gate electrode disposed on the top surface of the active region and a source/drain disposed in the active region;

an interlayer insulating film deposited on the MOS capacitor and the cell transistor;

a contact electrode connected to either the source/drain of the cell transistor or to the storage node electrode of the MOS capacitor through a contact hole in the interlayer insulating film;

a wire connected to the drain and the storage node electrode by the contact electrode; and

a bit line connected with the source by the contact electrode.

5. The DRAM cell of claim 4, wherein the MOS capacitor further includes a gap-fill layer filling a lower part of the trench with an insulating material.

6. The DRAM cell of claim 4, further comprising a power line for supplying a power voltage to the plate node electrode via an additional contact electrode of the interlayer insulating film.

7. The DRAM cell of claim 4, wherein the trench of the MOS capacitor is composed of curved trenches joined together by at least one linking trench.

8. The DRAM cell of claim 4, wherein a side wall spacer is disposed on side walls of the storage node electrode of the MOS capacitor and on side walls of the gate electrode of the cell transistor.