Fabricating a memory cell array

• US 20060054958A1
• Filed: 09/08/2005
• Published: 03/16/2006
• Est. Priority Date: 09/10/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Weis, Rolf, Gruening Von Schwerin, Ulrike
• Granted Patent: US 7,569,878 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.

Claims

1. A method for fabricating a memory cell array, wherein a plurality of memory cells, a plurality of word lines and a plurality of bit lines are formed in a semiconductor substrate, each memory cell comprising a storage capacitor to store an electric charge and a select transistor to drive the storage capacitor, the word lines are arranged in a first direction, and the bit lines are arranged in a second direction intersecting the first direction, the method comprising:

forming a first capacitor electrode, a storage dielectric and a second capacitor electrode of a storage capacitor for each memory cell;

forming at least one gate electrode from an electrically conductive gate material, a first source/drain region and a second source/drain region of a select transistor for each memory cell, such that the second capacitor electrode of the storage capacitor is connected to the first source/drain region of the select transistor, the first source/drain region is connected to the second source/drain region via a conductive channel region disposed in the semiconductor substrate, and the at least one gate electrode is disposed adjacent to the conductive channel region and is electrically insulated from the conductive channel region;

providing a plurality of word lines formed from an electrically conductive material, at least one word line being connected to a plurality of gate electrodes that are each assigned to memory cells arranged along the first direction, the at least one word line being configured to drive the gate electrodes connected to the at least one word line so as to facilitate a read operation;

providing a plurality of bit lines that are formed from an electrically conductive material and configured to transmit an electric charge that has been read; and

providing a plurality of bit line contacts, each bit line contact connecting the second source/drain region of the select transistor of a memory cell to a corresponding bit line;

wherein, for each memory cell, the at least one gate electrode is initially produced so as to be insulated from all other gate electrodes assigned to a corresponding word line, such that the corresponding word line provides the only connection for each gate electrode that is assigned to the corresponding word line.

2. The method of claim 1, wherein the storage capacitor of at least one memory cell comprises a trench capacitor formed in a capacitor trench of the semiconductor substrate, and the at least one gate electrode of the at least one memory cell is formed outside of the capacitor trench.

3. The method of claim 1, wherein the word lines are formed from an electrically conductive material that differs from the electrically conductive gate material of the at least one gate electrode.

4. The method of claim 1, wherein the memory cells are aligned with respect to each other in cell rows and cell columns, the storage capacitors and select transistors are arranged in a checkerboard pattern, the select transistors are assigned to diagonally adjacent first fields and the storage capacitors are assigned to intervening and diagonally adjacent second fields.

5. The method of claim 1, wherein the memory cells are aligned with respect to each other in cell rows and cell columns, and each storage capacitor is arranged in an adjacent pair with a corresponding select transistor such that at least two adjacent memory cells are assigned one common bit line contact.

6. The method of claim 1, wherein the storage capacitors are formed as stacked capacitors.

7. The method of claim 1, wherein the at least one gate electrode of each memory cell is formed by applying a layer of the electrically conductive gate material and then patterning the at least one gate electrode.

8. The method of claim 1, wherein the at least one gate electrode of each memory cell is formed by applying a layer of an auxiliary material, etching a region assigned to the at least one gate electrode in the auxiliary material and introducing the electrically conductive gate material into the etched region.

9. The method of claim 1, wherein the word lines are formed by applying a layer of the electrically conductive material and then patterning the word lines.

10. The method of claim 1, wherein the word lines are formed by applying a layer of an auxiliary material, etching regions assigned to the word lines in the auxiliary material and introducing the conductive material into the etched region.

11. The method of claim 1, wherein the word lines are formed after the first and second source/drain regions of the memory cells are formed.

12. The method of claim 1, wherein each of the first and second source/drain regions are formed such that a flow of current through the conductive channel region is substantially horizontal.

13. The method of claim 1, wherein forming the select transistor of each memory cell comprises producing a fin-like semiconductor substrate region in which the conductive channel region is formed.

14. The method of claim 13, wherein the at least one gate electrode of each memory cell is formed such that the at least one gate electrode surrounds at least two opposing sides of the corresponding conductive channel region.

15. The method of claim 14, wherein the at least one gate electrode is substantially U-shaped in cross-section and surrounds three sides of the corresponding conductive channel region.

16. The method of claim 1, wherein the second capacitor electrode is connected to the first source/drain region of the select transistor for each memory cell via a collecting region disposed within the semiconductor substrate.

17. The method of claim 1, wherein the second capacitor electrode is connected to the first source/drain region of the select transistor for each memory cell via a connecting region disposed above a surface of the semiconductor substrate.

18. A memory cell array comprising:

a plurality of word lines that are arranged in a first direction, and a plurality of bit lines that are arranged in a second direction intersecting the first direction; and

a plurality of memory cells that are at least partially formed in a semiconductor substrate, each memory cell comprising;

a storage capacitor to store an electric charge and comprising a first capacitor electrode, a storage dielectric and a second capacitor electrode; and

a select transistor to drive the storage capacitor and comprising at least one gate electrode formed of an electrically conductive gate material, a first source/drain region and a second source/drain region, the second capacitor electrode of the storage capacitor being connected to the first source/drain region of the select transistor, the first source/drain region being connected to the second source/drain region via a conductive channel region arranged in a fin-like semiconductor substrate region, the at least one gate electrode being arranged adjacent to and electrically insulated from the conductive channel region, and the at least one gate electrode surrounding at least two sides of the conductive channel region;

wherein a word line is connected to a plurality of gate electrodes that are formed in sections and are assigned to memory cells arranged along the first direction, and the word line is configured to drive the gate electrodes connected to the word line so as to trigger a read operation;

wherein the second source/drain region of the select transistor of each memory cell is connected via a bit line contact to a corresponding bit line that is configured to transmit an electric charge that has been read; and

wherein, in a cross section of the memory cell arrry through the conductive channel region, a bottom edge of each of the gate electrodes is arranged at a different height from bottom edges of the word lines, the height being defined as a distance measured perpendicular to a top surface of the substrate.

19. The memory cell array of claim 18, wherein the electrically conductive material of the word lines is different from the electrically conductive gate material of the gate electrodes.

20. The memory cell array of claim 18, wherein the memory cells are arranged in cell rows and cell columns, and the storage capacitors and select transistors are arranged in a checkerboard pattern, with the select transistors being assigned to diagonally adjacent first fields and the storage capacitors being assigned to intervening and diagonally adjacent second fields.

21. The memory cell array of claim 18, wherein the memory cells are arranged in cell rows and cell columns, and each storage capacitor is arranged in an adjacent pair with a corresponding select transistor such that at least two adjacent memory cells are assigned one common bit line contact.

22. The memory cell array of claim 18, wherein the storage capacitors comprise trench capacitors formed in trenches within the substrate.

23. The memory cell array of claim 18, wherein the storage capacitors comprise stacked capacitors.

24. The memory cell array of claim 18, wherein the second capacitor electrode is connected to the first source/drain region of the select transistor for each memory cell via a connecting region disposed within the semiconductor substrate.

25. The memory cell array of claim 18, wherein the second capacitor electrode is connected to the first source/drain region of the select transistor for each memory cell via a connecting region disposed above the top surface of the semiconductor substrate.

26. The memory cell array of claim 18, wherein the first and second source/drain regions are configured such that a flow of current through the conductive channel region is substantially horizontal.

27. The memory cell array of claim 18, wherein the at least one gate electrode of each memory cell is substantially U-shaped in cross-section and surrounds three sides of the corresponding conductive channel region.