Capacitor structure in trench structures of semiconductor devices and semiconductor devices comprising capacitor structures of this type and methods for fabricating the same

• US 20060054959A1
• Filed: 09/12/2005
• Published: 03/16/2006
• Est. Priority Date: 09/13/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Strack, Helmut, Mauder, Anton
• Granted Patent: US 7,795,660 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A capacitor structure includes: a number of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and a dielectric surrounding the conductive regions.

Claims

1-34. -34. (canceled)

35. A capacitor structure, comprising:

a plurality of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in a trench structure of a semiconductor device; and

a dielectric surrounding the conductive regions.

36. The capacitor structure of claim 35, wherein the dielectric comprises oxides and/or nitrides of the materials of the conductive regions.

37. The capacitor structure of claim 35, wherein the conductive regions comprise at least one of:

doped polysilicon, aluminum, titanium, hafnium, tantalum or alloys and/or chemical compounds thereof, titanium nitride, and hafnium nitride.

38. The capacitor structure of claim 35, wherein the dielectric comprises at least one of the following insulating materials:

SiO₂, Si₃N₄, TiO₂, HfO₂, Ta₂O₅, Al₂O₃, AlN, and mixtures thereof, the dielectric comprising a plurality of layers of different dielectrics of the insulating materials.

39. The capacitor structure of claim 35, wherein the stacked layers comprise a single conductive layer material, and the dielectric comprises an oxide and/or nitride of the single conductive layer material.

40. The capacitor structure of claim 35, wherein the stacked layers of the capacitor structure comprise electrically conducting titanium nitride and/or hafnium nitride and the dielectric comprises titanium oxide and/or hafnium oxide.

41. The capacitor structure of claim 35, wherein a thickness of the stacked layers and/or of insulation layers formed of the dielectric and disposed between the stacked layers varies in accordance with a predetermined potential distribution.

42. The capacitor structure of claim 35, wherein the trench structure includes trench walls comprising a dielectric coating containing SiO₂ and/or Si₃N₄.

43. The capacitor structure of claim 35, wherein the capacitor structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the same or opposite conduction type, the capacitor structure surrounding cells of the weakly doped semiconductor body region and the thickness (T_b) of the weakly doped semiconductor body region being greater than the depth (T_g) of the trench structure, such that a buffer layer comprising weakly doped semiconductor material of one conduction type is arranged between the capacitor structure and the highly doped substrate.

44. The capacitor structure of claim 43, wherein the cells are arranged in plate-like fashion one beside the other alternately with the capacitor structure on the highly doped substrate.

45. The capacitor structure of claim 43, wherein the cells are arranged in pillar-like fashion vertically one beside the other in a manner enveloped by the capacitor structure on the highly doped substrate.

55. A method for fabricating a layered capacitor of a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection;

b) anisotropically depositing an oxidizable and/or nitridable conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two;

c) completely oxidizing and/or nitriding a conductive layer deposited on the walls of the trench structure, while simultaneously oxidizing and/or nitriding a surface region of a conductive layer deposited at the bottom of the trench structure to form a dielectric intermediate layer; and

d) repeating b) and c) until the trench structure is filled to form the layered capacitor.

56. A method for fabricating a layered capacitor of a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection;

b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two;

c) depositing a dielectric material in the trench structure on the conductive material, such that a deposition rate at the walls is lower than at the bottom of the trench structure;

d) producing a selective protective layer on a layer made of the dielectric material at the bottom of the trench structure;

e) etching-back a layer sequence deposited on the walls up to the wall protection; and

f) repeating b) to e) until the trench structure is filled.

57. The method of claim 56, wherein undercuts of the capacitor structure formed by e) are filled by dielectric material.

58. The method of claim 56, wherein deposition parameters during the anisotropic application of conductive and/or dielectric material, for the purpose of setting different layer thicknesses (d_m, d_i), are varied in accordance with a predetermined potential profile in the stacking direction of the layered capacitor.

59. The method of claim 56, wherein etching-back with protection of the layer stack already formed is interposed when overhangs of deposited material are formed at an entrance to the trench structure.

60. The method of claim 56, wherein a) includes oxidizing in an oxygen and/or water vapor atmosphere.

61. The method of claim 56, wherein a) includes performing chemical vapor deposition the isotropic nitriding of the walls of the trench structure.

62. The method of claim 56, wherein b) includes sputtering.

63. The method of claim 56, wherein b) includes a directional vapor deposition.

64. The method of claim 56, wherein b) includes a directional ion beam deposition from a plasma.

65. The method of claims 56, further comprising removing the protective layer via plasma incineration.

66. The method of claim 56, wherein a photolithography method is performed for a masked application of the protective layer.

67. A method for fabricating a layered capacitor for a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure of the semiconductor device as wall protection;

b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at the bottom of the trench structure by at least a factor of two;

c) isotropically etching-back the conductive material until the walls are free of a conductive coating;

d) anisotropically depositing an insulating material in the trench structure, a deposition rate at the walls being lower than at the bottom of the trench structure by at least a factor of two; and

e) repeating b) to d) until the trench structure is filled to form a layered capacitor.