Five-level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter

• US 20060055581A1
• Filed: 08/02/2005
• Published: 03/16/2006
• Est. Priority Date: 08/20/2004
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Deval, Philippe
• Granted Patent: US 7,102,558 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: H03M 3/434 with multi-level feedback
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path

Abstract

A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF/2, 0, −C*VREF/2 and −C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−VREF/2 and A*VIN−VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Claims

1. A reference voltage switching arrangement for a five level feed-back digital-to-analog converter used with a switched capacitor sigma-delta analog-to-digital converter, said reference voltage switching arrangement comprising:

a plus reference voltage capacitor having a capacitance of C/2;

a minus reference voltage capacitor having a capacitance of C/2;

a first pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively;

a second pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively; and

a third switch adapted for switchably coupling the plus and minus reference voltage capacitors together, wherein the first pair of switches, the second pair of switches, and the third switch are sequenced in a charge phase and a transfer phase to produce five equally distributed charge levels of C*VREF, C*VREF/2, 0, −

C*VREF/2 and −

C*VREF, where VREF is a reference voltage.

2. The reference voltage switching arrangement according to claim 1, wherein the charge phase and transfer phase switching sequences of the first pair of switches, the second pair of switches, and the third switch do not overlap.

3. The reference voltage switching arrangement according to claim 1, wherein for the charge level of C*VREF:

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase; and

the third switch is open during the charge phase and the transfer phase.

4. The reference voltage switching arrangement according to claim 1, wherein for the charge level of C*VREF/2:

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and the transfer phase; and

the third switch is open during the charge phase and closed during the transfer phase.

5. The reference voltage switching arrangement according to claim 1, wherein for the charge level of 0:

the first pair of switches are open during the charge phase and the transfer phase;

the second pair of switches are open during the charge phase and the transfer phase; and

the third switch is closed during the charge phase and the transfer phase.

6. The reference voltage switching arrangement according to claim 1, wherein for the charge level of −

C*VREF/2;

the first pair of switches are open during the charge phase and the transfer phase;

the second pair of switches are closed during the charge phase and open during the transfer phase; and

the third switch is open during the charge phase and closed during the transfer phase.

7. The reference voltage switching arrangement according to claim 1, wherein for the charge level of −

C*VREF;

the first pair of switches are open during the charge phase and closed during the transfer phase;

the second pair of switches are closed during the charge phase and open during the transfer phase; and

the third switch is open during the charge phase and the transfer phase.

8. A five level feed-back digital-to-analog converter for a switched capacitor sigma-delta analog-to-digital converter, said five level feed-back digital-to-analog converter comprising:

a plus input voltage capacitor having a capacitance of A*C/2;

a minus input voltage capacitor having a capacitance of A*C/2;

a first pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to plus and minus input voltages, respectively;

a second pair of switches adapted for switchably coupling the plus and minus input voltage capacitors to the minus and the plus input voltages, respectively;

a plus reference voltage capacitor having a capacitance of C/2;

a minus reference voltage capacitor having a capacitance of C/2;

a fifth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively;

a sixth pair of switches adapted for switchably coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively; and

a seventh switch adapted for switchably coupling the plus and minus reference voltage capacitors together;

a third plurality of switches coupled to the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors, and adapted for switchably coupling a common mode voltage, VCM, to these capacitors; and

a fourth pair of switches adapted for coupling the plus and minus input voltage capacitors and the plus and minus reference voltage capacitors to a differential input of an amplifier,

wherein the switches are sequenced in a charge phase and a transfer phase to produce five equally distributed voltage outputs from the amplifier of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−

VREF/2 and A*VIN−

VREF, where A is gain, VIN is an input voltage, and VREF is a reference voltage.

9. The five level feed-back digital-to-analog converter according to claim 8, wherein the charge phase and transfer phase switching sequences of the switches do not overlap.

10. The five level feed-back digital-to-analog converter according to claim 8, wherein for the voltage output of A*VIN+VREF:

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase;

the third plurality of switches are closed during the charge phase and open during the transfer phase;

the fourth pair of switches are open during the charge phase and closed during the transfer phase;

the fifth pair of switches are closed during the charge phase and open during the transfer phase;

the sixth pair of switches are open during the charge phase and closed during the transfer phase; and

the seventh switch is open during the charge phase and the transfer phase.

11. The five level feed-back digital-to-analog converter according to claim 8, wherein for the voltage output of A*VIN+VREF/2:

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase;

the third plurality of switches are closed during the charge phase and open during the transfer phase;

the fourth pair of switches are open during the charge phase and closed during the transfer phase;

the fifth pair of switches are closed during the charge phase and open during the transfer phase;

the sixth pair of switches are open during the charge phase and the transfer phase; and

the seventh switch is open during the charge phase and closed during the transfer phase.

12. The five level feed-back digital-to-analog converter according to claim 8, wherein for the voltage output of A*VIN+0:

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase;

the third plurality of switches are closed during the charge phase and open during the transfer phase;

the fourth pair of switches are open during the charge phase and closed during the transfer phase;

the fifth pair of switches are open during the charge phase and the transfer phase;

the sixth pair of switches are open during the charge phase and the transfer phase; and

the seventh switch is closed during the charge phase and the transfer phase.

13. The five level feed-back digital-to-analog converter according to claim 8, wherein for the voltage output of A*VIN−

VREF/2;

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase;

the third plurality of switches are closed during the charge phase and open during the transfer phase;

the fourth pair of switches are open during the charge phase and closed during the transfer phase;

the fifth pair of switches are open during the charge phase and the transfer phase;

the sixth pair of switches are closed during the charge phase and open during the transfer phase; and

the seventh switch is open during the charge phase and closed during the transfer phase.

14. The five level feed-back digital-to-analog converter according to claim 8, wherein for the charge level of A*VIN−

VREF;

the first pair of switches are closed during the charge phase and open during the transfer phase;

the second pair of switches are open during the charge phase and closed during the transfer phase;

the third plurality of switches are closed during the charge phase and open during the transfer phase;

the fourth pair of switches are open during the charge phase and closed during the transfer phase;

the fifth pair of switches are open during the charge phase and closed during the transfer phase;

the sixth pair of switches are closed during the charge phase and open during the transfer phase; and

the seventh switch is open during the charge phase and the transfer phase.

15. The five level feed-back digital-to-analog converter according to claim 8, wherein the amplifier is a differential input and output operational amplifier.

16. A method for producing five reference voltage levels in a feed-back digital-to-analog converter used with a switched capacitor sigma-delta analog-to-digital converter, said method comprising the steps of:

providing a plus reference voltage capacitor having a capacitance of C/2;

providing a minus reference voltage capacitor having a capacitance of C/2;

producing a charge level of C*VREF by

coupling the plus and minus reference voltage capacitors to plus and minus reference voltages, respectively, during a charge phase, and

coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during a transfer phase;

producing a charge level of C*VREF/2 by

coupling the plus and minus reference voltage capacitors to the plus and minus reference voltages, respectively, during the charge phase, and

coupling the plus and minus reference voltage capacitors together, during the transfer phase;

producing a charge level of 0 by

coupling the plus and minus reference voltage capacitors together during the charge phase and the transfer phase;

producing a charge level of −

C*VREF/2 by

coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during the charge phase; and

coupling the plus and minus reference voltage capacitors together, during the transfer phase; and

producing a charge level of −

C*VREF by

coupling the plus and minus reference voltage capacitors to the minus and the plus reference voltages, respectively, during the charge phase; and

coupling the plus and minus reference voltage capacitors to the plus and minus reference voltages, respectively, during the transfer phase.

17. The method according to claim 16, further comprising the steps of:

providing a plus input voltage capacitor having a capacitance of A*C/2;

providing a minus input voltage capacitor having a capacitance of A*C/2;

coupling the plus and minus input voltage capacitors to plus and minus input voltages, respectively, during the charge phase;

coupling the plus and minus input voltage capacitors to the minus and plus input voltages, respectively, during the transfer phase;

coupling the plus and minus reference voltage capacitors and the plus and minus input voltage capacitors to a common mode voltage during the charge phase; and

coupling the plus and minus reference voltage capacitors and the plus and minus input voltage capacitors to a differential input of an amplifier during the transfer phase,

wherein the amplifier produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN−

VREF/2 and A*VIN−

V_REF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.